1217 lines
28 KiB
Plaintext
1217 lines
28 KiB
Plaintext
/*
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* Copyright 2021,2023-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/pm/imx_spc.h>
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#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
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/ {
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chosen {
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zephyr,entropy = &caam;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m7";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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d-cache-line-size = <32>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <1>;
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d-cache-line-size = <32>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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power-states {
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/*
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* Power states are managed with set points (see page 30-35 of RT1170
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* datasheet). These set points correspond to various power
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* savings, and associated transition (residency) times.
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*
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* Set points 1 and 10 were chosen as sane defaults to offer
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* limited power savings and quick transitions when entering idle for
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* short periods, and better power savings with longer transition
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* times for long idle periods
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*/
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idle: set_point_1_wait {
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/* idle corresponds to set point 1 (wait) for RT1170 */
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compatible = "zephyr,power-state";
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power-state-name="runtime-idle";
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substate-id = <IMX_SPC_SET_POINT_1_WAIT>;
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min-residency-us = <100>;
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};
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suspend: set_point_10_suspend {
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/* suspend corresponds to set point 10 for RT1170 */
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compatible = "zephyr,power-state";
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power-state-name="suspend-to-idle";
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substate-id = <IMX_SPC_SET_POINT_10_SUSPEND>;
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min-residency-us = <5000>;
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exit-latency-us = <500>;
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};
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};
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};
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xtal: xtal-osc {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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soc {
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flexspi: spi@400cc000 {
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compatible = "nxp,imx-flexspi";
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reg = <0x400cc000 0x4000>;
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interrupts = <130 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0>;
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};
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flexspi2: spi@400d0000 {
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compatible = "nxp,imx-flexspi";
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reg = <0x400d0000 0x4000>;
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interrupts = <131 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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clocks = <&ccm IMX_CCM_FLEXSPI2_CLK 0x0 0>;
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};
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semc: semc0@400d4000 {
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compatible = "nxp,imx-semc";
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reg = <0x400d4000 0x4000>;
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interrupts = <132 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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/* GPT1 is used for the hardware timer, not as a standard counter */
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gpt_hw_timer: gpt@400ec000 {
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compatible = "nxp,gpt-hw-timer";
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reg = <0x400ec000 0x4000>;
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interrupts = <119 0>;
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status = "disabled";
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};
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gpt2: gpt@400f0000 {
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compatible = "nxp,imx-gpt";
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reg = <0x400f0000 0x4000>;
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interrupts = <120 0>;
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gptfreq = <24000000>;
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clocks = <&ccm IMX_CCM_GPT_CLK 0x41 0>;
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};
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gpt3: gpt@400f4000 {
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compatible = "nxp,imx-gpt";
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reg = <0x400f4000 0x4000>;
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interrupts = <121 0>;
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gptfreq = <24000000>;
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clocks = <&ccm IMX_CCM_GPT_CLK 0x42 0>;
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};
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gpt4: gpt@400f8000 {
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compatible = "nxp,imx-gpt";
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reg = <0x400f8000 0x4000>;
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interrupts = <122 0>;
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gptfreq = <24000000>;
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clocks = <&ccm IMX_CCM_GPT_CLK 0x43 0>;
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};
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gpt5: gpt@400fc000 {
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compatible = "nxp,imx-gpt";
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reg = <0x400fc000 0x4000>;
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interrupts = <123 0>;
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gptfreq = <24000000>;
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clocks = <&ccm IMX_CCM_GPT_CLK 0x44 0>;
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};
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gpt6: gpt@40100000 {
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compatible = "nxp,imx-gpt";
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reg = <0x40100000 0x4000>;
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interrupts = <124 0>;
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gptfreq = <24000000>;
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clocks = <&ccm IMX_CCM_GPT_CLK 0x45 0>;
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};
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ccm: ccm@40cc0000 {
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compatible = "nxp,imx-ccm-rev2";
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reg = <0x40cc0000 0x4000>;
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#clock-cells = <3>;
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};
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gpio1: gpio@4012c000 {
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compatible = "nxp,imx-gpio";
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reg = <0x4012c000 0x4000>;
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interrupts = <100 0>, <101 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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/*
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* Note that CM7 and CM4 cores do not have the same memory addresses
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* for GPIO2 and GPIO3, so those peripherals are defined in the SOC
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* specific DTS files
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*/
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gpio4: gpio@40138000 {
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compatible = "nxp,imx-gpio";
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reg = <0x40138000 0x4000>;
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interrupts = <106 0>, <107 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio5: gpio@4013c000 {
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compatible = "nxp,imx-gpio";
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reg = <0x4013c000 0x4000>;
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interrupts = <108 0>, <109 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio6: gpio@40140000 {
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compatible = "nxp,imx-gpio";
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reg = <0x40140000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio7: gpio@40c5c000 {
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compatible = "nxp,imx-gpio";
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reg = <0x40c5c000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio8: gpio@40c60000 {
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compatible = "nxp,imx-gpio";
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reg = <0x40c60000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio9: gpio@40c64000 {
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compatible = "nxp,imx-gpio";
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reg = <0x40c64000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio10: gpio@40c68000 {
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compatible = "nxp,imx-gpio";
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reg = <0x40c68000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio11: gpio@40c6c000 {
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compatible = "nxp,imx-gpio";
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reg = <0x40c6c000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio12: gpio@40c70000 {
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compatible = "nxp,imx-gpio";
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reg = <0x40c70000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio13: gpio@40ca0000 {
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compatible = "nxp,imx-gpio";
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reg = <0x40ca0000 0x4000>;
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interrupts = <93 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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lpi2c1: i2c@40104000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40104000 0x4000>;
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interrupts = <32 0>;
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clocks = <&ccm IMX_CCM_LPI2C1_CLK 0x70 6>;
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status = "disabled";
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};
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lpi2c2: i2c@40108000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40108000 0x4000>;
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interrupts = <33 0>;
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clocks = <&ccm IMX_CCM_LPI2C2_CLK 0x70 8>;
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status = "disabled";
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};
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lpi2c3: i2c@4010c000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4010c000 0x4000>;
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interrupts = <34 0>;
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clocks = <&ccm IMX_CCM_LPI2C3_CLK 0x70 10>;
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status = "disabled";
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};
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lpi2c4: i2c@40110000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40110000 0x4000>;
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interrupts = <35 0>;
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clocks = <&ccm IMX_CCM_LPI2C4_CLK 0x80 24>;
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status = "disabled";
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};
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lpi2c5: i2c@40c34000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40c34000 0x4000>;
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interrupts = <36 0>;
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clocks = <&ccm IMX_CCM_LPI2C5_CLK 0x80 24>;
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status = "disabled";
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};
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lpi2c6: i2c@40c38000 {
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compatible = "nxp,imx-lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40c38000 0x4000>;
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interrupts = <37 0>;
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clocks = <&ccm IMX_CCM_LPI2C6_CLK 0x80 24>;
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status = "disabled";
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};
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iomuxc: iomuxc@400e8000 {
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compatible = "nxp,imx-iomuxc";
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reg = <0x400e8000 0x4000>;
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status = "okay";
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pinctrl: pinctrl {
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status = "okay";
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compatible = "nxp,mcux-rt11xx-pinctrl";
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};
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};
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iomuxc_lpsr: iomuxc_lpsr@40c08000 {
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compatible = "nxp,mcux-rt-pinctrl";
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reg = <0x40c08000 0x4000>;
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status = "disabled";
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};
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iomuxc_lpsr_gpr: iomuxc_lpsr_gpr@40c08000 {
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compatible = "nxp,imx-gpr";
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reg = <0x40c08000 0x4000>;
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#pinmux-cells = <2>;
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};
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lcdif: display-controller@40804000 {
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compatible = "nxp,imx-elcdif";
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reg = <0x40804000 0x4000>;
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interrupts = <54 0>;
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status = "disabled";
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nxp,pxp = <&pxp>;
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};
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mipi_dsi: mipi-dsi@4080c000 {
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compatible = "nxp,imx-mipi-dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4080c000 0x200>,
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<0x4080c200 0x80>,
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<0x4080c280 0x80>,
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<0x4080c300 0x200>;
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interrupts = <59 1>;
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status = "disabled";
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};
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lpspi1: spi@40114000 {
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compatible = "nxp,imx-lpspi";
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reg = <0x40114000 0x4000>;
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interrupts = <38 3>;
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status = "disabled";
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clocks = <&ccm IMX_CCM_LPSPI1_CLK 0x6c 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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lpspi2: spi@40118000 {
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compatible = "nxp,imx-lpspi";
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reg = <0x40118000 0x4000>;
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interrupts = <39 3>;
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status = "disabled";
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clocks = <&ccm IMX_CCM_LPSPI2_CLK 0x6c 2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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lpspi3: spi@4011c000 {
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compatible = "nxp,imx-lpspi";
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reg = <0x4011c000 0x4000>;
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interrupts = <40 3>;
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status = "disabled";
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clocks = <&ccm IMX_CCM_LPSPI3_CLK 0x6c 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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lpspi4: spi@40120000 {
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compatible = "nxp,imx-lpspi";
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reg = <0x40120000 0x4000>;
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interrupts = <41 3>;
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status = "disabled";
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clocks = <&ccm IMX_CCM_LPSPI4_CLK 0x6c 6>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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lpspi5: spi@40c2c000 {
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compatible = "nxp,imx-lpspi";
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reg = <0x40c2c000 0x4000>;
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interrupts = <42 3>;
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status = "disabled";
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clocks = <&ccm IMX_CCM_LPSPI5_CLK 0x6c 6>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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lpspi6: spi@40c30000 {
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compatible = "nxp,imx-lpspi";
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reg = <0x40c30000 0x4000>;
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interrupts = <43 3>;
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status = "disabled";
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clocks = <&ccm IMX_CCM_LPSPI6_CLK 0x6c 6>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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lpuart1: uart@4007c000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x4007c000 0x4000>;
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interrupts = <20 0>;
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clocks = <&ccm IMX_CCM_LPUART1_CLK 0x7c 24>;
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status = "disabled";
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};
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lpuart2: uart@40080000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x40080000 0x4000>;
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interrupts = <21 0>;
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clocks = <&ccm IMX_CCM_LPUART2_CLK 0x68 28>;
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status = "disabled";
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};
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lpuart3: uart@40084000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x40084000 0x4000>;
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interrupts = <22 0>;
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clocks = <&ccm IMX_CCM_LPUART3_CLK 0x68 12>;
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status = "disabled";
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};
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lpuart4: uart@40088000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x40088000 0x4000>;
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interrupts = <23 0>;
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clocks = <&ccm IMX_CCM_LPUART4_CLK 0x6c 24>;
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status = "disabled";
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};
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lpuart5: uart@4008c000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x4008c000 0x4000>;
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interrupts = <24 0>;
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clocks = <&ccm IMX_CCM_LPUART5_CLK 0x74 2>;
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status = "disabled";
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};
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lpuart6: uart@40090000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x40090000 0x4000>;
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interrupts = <25 0>;
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clocks = <&ccm IMX_CCM_LPUART6_CLK 0x74 6>;
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status = "disabled";
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};
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lpuart7: uart@40094000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x40094000 0x4000>;
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interrupts = <26 0>;
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clocks = <&ccm IMX_CCM_LPUART7_CLK 0x7c 26>;
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status = "disabled";
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};
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lpuart8: uart@40098000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x40098000 0x4000>;
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interrupts = <27 0>;
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clocks = <&ccm IMX_CCM_LPUART8_CLK 0x80 14>;
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status = "disabled";
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};
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lpuart9: uart@4009c000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x4009c000 0x4000>;
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interrupts = <28 0>;
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clocks = <&ccm IMX_CCM_LPUART9_CLK 0x80 14>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart10: uart@400a0000 {
|
|
compatible = "nxp,kinetis-lpuart";
|
|
reg = <0x400a0000 0x4000>;
|
|
interrupts = <29 0>;
|
|
clocks = <&ccm IMX_CCM_LPUART10_CLK 0x80 14>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart11: uart@40c24000 {
|
|
compatible = "nxp,kinetis-lpuart";
|
|
reg = <0x40c24000 0x4000>;
|
|
interrupts = <30 0>;
|
|
clocks = <&ccm IMX_CCM_LPUART11_CLK 0x80 14>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart12: uart@40c28000 {
|
|
compatible = "nxp,kinetis-lpuart";
|
|
reg = <0x40c28000 0x4000>;
|
|
interrupts = <31 0>;
|
|
clocks = <&ccm IMX_CCM_LPUART12_CLK 0x80 14>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexpwm1: flexpwm@4018c000 {
|
|
compatible = "nxp,flexpwm";
|
|
reg = <0x4018c000 0x4000>;
|
|
interrupts = <129 0>;
|
|
|
|
flexpwm1_pwm0: flexpwm1_pwm0 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <0>;
|
|
interrupts = <125 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexpwm1_pwm1: flexpwm1_pwm1 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <1>;
|
|
interrupts = <126 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexpwm1_pwm2: flexpwm1_pwm2 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <2>;
|
|
interrupts = <127 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexpwm1_pwm3: flexpwm1_pwm3 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <3>;
|
|
interrupts = <128 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flexpwm2: flexpwm@40190000 {
|
|
compatible = "nxp,flexpwm";
|
|
reg = <0x40190000 0x4000>;
|
|
interrupts = <181 0>;
|
|
|
|
flexpwm2_pwm0: flexpwm2_pwm0 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <0>;
|
|
interrupts = <177 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexpwm2_pwm1: flexpwm2_pwm1 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <1>;
|
|
interrupts = <178 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexpwm2_pwm2: flexpwm2_pwm2 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <2>;
|
|
interrupts = <179 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexpwm2_pwm3: flexpwm2_pwm3 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <3>;
|
|
interrupts = <180 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flexpwm3: flexpwm@40194000 {
|
|
compatible = "nxp,flexpwm";
|
|
reg = <0x40194000 0x4000>;
|
|
interrupts = <186 0>;
|
|
|
|
flexpwm3_pwm0: flexpwm3_pwm0 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <0>;
|
|
interrupts = <182 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexpwm3_pwm1: flexpwm3_pwm1 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <1>;
|
|
interrupts = <183 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexpwm3_pwm2: flexpwm3_pwm2 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <2>;
|
|
interrupts = <184 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexpwm3_pwm3: flexpwm3_pwm3 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <3>;
|
|
interrupts = <185 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flexpwm4: flexpwm@40198000 {
|
|
compatible = "nxp,flexpwm";
|
|
reg = <0x40198000 0x4000>;
|
|
interrupts = <191 0>;
|
|
|
|
flexpwm4_pwm0: flexpwm4_pwm0 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <0>;
|
|
interrupts = <187 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexpwm4_pwm1: flexpwm4_pwm1 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <1>;
|
|
interrupts = <188 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexpwm4_pwm2: flexpwm4_pwm2 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <2>;
|
|
interrupts = <189 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexpwm4_pwm3: flexpwm4_pwm3 {
|
|
compatible = "nxp,imx-pwm";
|
|
index = <3>;
|
|
interrupts = <190 0>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
|
|
nxp,prescaler = <128>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
enet: ethernet@40424000 {
|
|
compatible = "nxp,enet";
|
|
reg = <0x40424000 0x628>;
|
|
clocks = <&ccm IMX_CCM_ENET_CLK 0 0>;
|
|
enet_mac: ethernet {
|
|
compatible = "nxp,enet-mac";
|
|
interrupts = <137 0>;
|
|
interrupt-names = "COMMON";
|
|
nxp,mdio = <&enet_mdio>;
|
|
nxp,ptp-clock = <&enet_ptp_clock>;
|
|
status = "disabled";
|
|
};
|
|
enet_mdio: mdio {
|
|
compatible = "nxp,enet-mdio";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
enet_ptp_clock: ptp_clock {
|
|
compatible = "nxp,enet-ptp-clock";
|
|
interrupts = <138 0>;
|
|
status = "disabled";
|
|
clocks = <&ccm IMX_CCM_ENET_PLL 0 0>;
|
|
};
|
|
};
|
|
|
|
/*
|
|
* enet1g peripheral to use with kinetis-ethernet (eth_mcux) driver
|
|
* just like the enet peripheral (i.e. only 10/100Mbit for now)
|
|
*/
|
|
enet1g: ethernet@40420000 {
|
|
compatible = "nxp,kinetis-ethernet";
|
|
reg = <0x40420000 0x628>;
|
|
interrupts = <141 0>;
|
|
interrupt-names = "COMMON";
|
|
status = "disabled";
|
|
phy-addr = <1>;
|
|
ptp1g: ptp {
|
|
compatible = "nxp,kinetis-ptp";
|
|
status = "disabled";
|
|
interrupts = <142 0>;
|
|
interrupt-names = "IEEE1588_TMR";
|
|
};
|
|
};
|
|
|
|
caam: caam@40440000 {
|
|
compatible = "nxp,imx-caam";
|
|
reg = <0x40440000 0x81000>;
|
|
interrupts = <69 0>, <70 0>, <71 0>,
|
|
<72 0>, <73 0>, <74 0>;
|
|
status = "okay";
|
|
};
|
|
|
|
usb1: usbd@40430000 {
|
|
compatible = "nxp,ehci";
|
|
reg = <0x40430000 0x200>;
|
|
interrupts = <136 1>;
|
|
interrupt-names = "usb_otg";
|
|
clocks = <&xtal>;
|
|
num-bidir-endpoints = <8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2: usbd@4042c000 {
|
|
compatible = "nxp,ehci";
|
|
reg = <0x4042c000 0x200>;
|
|
interrupts = <135 1>;
|
|
interrupt-names = "usb_otg";
|
|
clocks = <&xtal>;
|
|
num-bidir-endpoints = <8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc1: usdhc@40418000 {
|
|
compatible = "nxp,imx-usdhc";
|
|
reg = <0x40418000 0x4000>;
|
|
status = "disabled";
|
|
interrupts = <133 0>;
|
|
clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
|
|
max-current-330 = <1020>;
|
|
max-current-180 = <1020>;
|
|
max-bus-freq = <208000000>;
|
|
min-bus-freq = <400000>;
|
|
};
|
|
|
|
usdhc2: usdhc@4041c000 {
|
|
compatible = "nxp,imx-usdhc";
|
|
reg = <0x4041c000 0x4000>;
|
|
status = "disabled";
|
|
interrupts = <134 0>;
|
|
clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
|
|
max-current-330 = <1020>;
|
|
max-current-180 = <1020>;
|
|
max-bus-freq = <208000000>;
|
|
min-bus-freq = <400000>;
|
|
};
|
|
|
|
csi: csi@40800000 {
|
|
compatible = "nxp,imx-csi";
|
|
reg = <0x40800000 0x4000>;
|
|
interrupts = <56 1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexcan1: can@400c4000 {
|
|
compatible = "nxp,flexcan-fd", "nxp,flexcan";
|
|
reg = <0x400c4000 0x1000>;
|
|
interrupts = <44 0>, <45 0>;
|
|
interrupt-names = "common", "error";
|
|
clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>;
|
|
clk-source = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexcan2: can@400c8000 {
|
|
compatible = "nxp,flexcan-fd", "nxp,flexcan";
|
|
reg = <0x400c8000 0x1000>;
|
|
interrupts = <46 0>, <47 0>;
|
|
interrupt-names = "common", "error";
|
|
clocks = <&ccm IMX_CCM_CAN2_CLK 0x68 18>;
|
|
clk-source = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flexcan3: can@40c3c000 {
|
|
compatible = "nxp,flexcan-fd", "nxp,flexcan";
|
|
reg = <0x40c3c000 0x1000>;
|
|
interrupts = <48 0>, <49 0>;
|
|
interrupt-names = "common", "error";
|
|
clocks = <&ccm IMX_CCM_CAN3_CLK 0x84 6>;
|
|
clk-source = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog1: wdog@40030000 {
|
|
compatible = "nxp,imx-wdog";
|
|
reg = <0x40030000 0xA>;
|
|
status = "disabled";
|
|
interrupts = <112 0>;
|
|
};
|
|
|
|
ocram: ocram@20200000 {
|
|
compatible = "zephyr,memory-region", "mmio-sram";
|
|
zephyr,memory-region = "OCRAM";
|
|
reg = <0x20200000 DT_SIZE_K(256)>;
|
|
};
|
|
|
|
ocram1: ocram@20240000 {
|
|
compatible = "zephyr,memory-region", "mmio-sram";
|
|
zephyr,memory-region = "OCRAM1";
|
|
reg = <0x20240000 DT_SIZE_K(512)>;
|
|
};
|
|
|
|
ocram2: ocram@202c0000 {
|
|
compatible = "zephyr,memory-region", "mmio-sram";
|
|
zephyr,memory-region = "OCRAM2";
|
|
reg = <0x202c0000 DT_SIZE_K(512)>;
|
|
};
|
|
|
|
lpadc0: lpadc@40050000 {
|
|
compatible = "nxp,lpc-lpadc";
|
|
reg = <0x40050000 0x304>;
|
|
interrupts = <88 0>;
|
|
status = "disabled";
|
|
clk-divider = <8>;
|
|
clk-source = <0>;
|
|
voltage-ref= <1>;
|
|
calibration-average = <128>;
|
|
power-level = <0>;
|
|
offset-value-a = <10>;
|
|
offset-value-b = <10>;
|
|
#io-channel-cells = <1>;
|
|
clocks = <&ccm IMX_CCM_LPADC1_CLK 0 0>;
|
|
};
|
|
|
|
lpadc1: lpadc@40054000 {
|
|
compatible = "nxp,lpc-lpadc";
|
|
reg = <0x40054000 0x304>;
|
|
interrupts = <89 0>;
|
|
status = "disabled";
|
|
clk-divider = <8>;
|
|
clk-source = <0>;
|
|
voltage-ref= <1>;
|
|
calibration-average = <128>;
|
|
power-level = <1>;
|
|
offset-value-a = <10>;
|
|
offset-value-b = <10>;
|
|
#io-channel-cells = <1>;
|
|
clocks = <&ccm IMX_CCM_LPADC2_CLK 0 0>;
|
|
};
|
|
|
|
acmp1: cmp@401a4000 {
|
|
compatible = "nxp,kinetis-acmp";
|
|
reg = <0x401a4000 0x4000>;
|
|
interrupts = <157 0>;
|
|
status = "disabled";
|
|
#io-channel-cells = <2>;
|
|
};
|
|
|
|
acmp2: cmp@401a8000 {
|
|
compatible = "nxp,kinetis-acmp";
|
|
reg = <0x401a8000 0x4000>;
|
|
interrupts = <158 0>;
|
|
status = "disabled";
|
|
#io-channel-cells = <2>;
|
|
};
|
|
|
|
acmp3: cmp@401ac000 {
|
|
compatible = "nxp,kinetis-acmp";
|
|
reg = <0x401ac000 0x4000>;
|
|
interrupts = <159 0>;
|
|
status = "disabled";
|
|
#io-channel-cells = <2>;
|
|
};
|
|
|
|
acmp4: cmp@401b0000 {
|
|
compatible = "nxp,kinetis-acmp";
|
|
reg = <0x401b0000 0x4000>;
|
|
interrupts = <160 0>;
|
|
status = "disabled";
|
|
#io-channel-cells = <2>;
|
|
};
|
|
|
|
anatop: anatop@40c84000 {
|
|
compatible = "nxp,imx-anatop";
|
|
reg = <0x40c84000 0x4000>;
|
|
#clock-cells = <4>;
|
|
#pll-clock-cells = <3>;
|
|
};
|
|
|
|
edma0: dma-controller@40070000 {
|
|
#dma-cells = <2>;
|
|
compatible = "nxp,mcux-edma";
|
|
dma-channels = <32>;
|
|
dma-requests = <208>;
|
|
nxp,mem2mem;
|
|
nxp,a_on;
|
|
reg = <0x40070000 0x4000>,
|
|
<0x40074000 0x4000>;
|
|
clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
|
|
status = "disabled";
|
|
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
|
<4 0>, <5 0>, <6 0>, <7 0>,
|
|
<8 0>, <9 0>, <10 0>, <11 0>,
|
|
<12 0>, <13 0>, <14 0>, <15 0>,
|
|
<16 0>;
|
|
irq-shared-offset = <16>;
|
|
};
|
|
|
|
edma_lpsr0: dma-controller@40c14000 {
|
|
#dma-cells = <2>;
|
|
compatible = "nxp,mcux-edma";
|
|
dma-channels = <32>;
|
|
dma-requests = <208>;
|
|
nxp,mem2mem;
|
|
nxp,a_on;
|
|
reg = <0x40c14000 0x4000>,
|
|
<0x40c18000 0x4000>;
|
|
clocks = <&ccm IMX_CCM_EDMA_LPSR_CLK 0x7C 0x000000C0>;
|
|
status = "disabled";
|
|
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
|
|
<4 0>, <5 0>, <6 0>, <7 0>,
|
|
<8 0>, <9 0>, <10 0>, <11 0>,
|
|
<12 0>, <13 0>, <14 0>, <15 0>,
|
|
<16 0>;
|
|
irq-shared-offset = <16>;
|
|
};
|
|
|
|
pxp: pxp@40814000 {
|
|
compatible = "nxp,pxp";
|
|
reg = <0x40814000 0x4000>;
|
|
interrupts = <57 0>;
|
|
status = "disabled";
|
|
#dma-cells = <0>;
|
|
};
|
|
|
|
iomuxcgpr: iomuxcgpr@400e4000 {
|
|
compatible = "nxp,imx-gpr";
|
|
reg = <0x400e4000 0x4000>;
|
|
#pinmux-cells = <2>;
|
|
};
|
|
|
|
sai1: sai@40404000 {
|
|
compatible = "nxp,mcux-i2s";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#pinmux-cells = <2>;
|
|
reg = <0x40404000 0x4000>;
|
|
clocks = <&ccm IMX_CCM_SAI1_CLK 0x2004 4>;
|
|
/* Source from audio PLL */
|
|
clock-mux = <4>;
|
|
pre-div = <0>;
|
|
podf = <4>;
|
|
pll-clocks = <&anatop 0 0 0>,
|
|
<&anatop 0 0 30>,
|
|
<&anatop 0 0 1>,
|
|
<&anatop 0 0 77>,
|
|
<&anatop 0 0 100>;
|
|
pll-clock-names = "src", "lp", "pd", "num", "den";
|
|
pinmuxes = <&iomuxcgpr 0x0 0x100>;
|
|
interrupts = <76 0>;
|
|
nxp,tx-channel = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sai2: sai@40408000 {
|
|
compatible = "nxp,mcux-i2s";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#pinmux-cells = <2>;
|
|
reg = <0x40408000 0x4000>;
|
|
clocks = <&ccm IMX_CCM_SAI2_CLK 0x2084 4>;
|
|
/* Source from audio PLL */
|
|
clock-mux = <4>;
|
|
pre-div = <0>;
|
|
podf = <63>;
|
|
pll-clocks = <&anatop 0 0 0>,
|
|
<&anatop 0 0 30>,
|
|
<&anatop 0 0 1>,
|
|
<&anatop 0 0 77>,
|
|
<&anatop 0 0 100>;
|
|
pll-clock-names = "src", "lp", "pd", "num", "den";
|
|
pinmuxes = <&iomuxcgpr 0x4 0x100>;
|
|
interrupts = <77 0>;
|
|
nxp,tx-channel = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sai3: sai@4040c000 {
|
|
compatible = "nxp,mcux-i2s";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#pinmux-cells = <2>;
|
|
reg = <0x4040c000 0x4000>;
|
|
clocks = <&ccm IMX_CCM_SAI3_CLK 0x2104 4>;
|
|
/* Source from audio PLL */
|
|
clock-mux = <4>;
|
|
pre-div = <0>;
|
|
podf = <63>;
|
|
pll-clocks = <&anatop 0 0 0>,
|
|
<&anatop 0 0 30>,
|
|
<&anatop 0 0 1>,
|
|
<&anatop 0 0 77>,
|
|
<&anatop 0 0 100>;
|
|
pll-clock-names = "src", "lp", "pd", "num", "den";
|
|
pinmuxes = <&iomuxcgpr 0x8 0x100>;
|
|
interrupts = <78 0>, <79 0>;
|
|
nxp,tx-channel = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sai4: sai@40c40000 {
|
|
compatible = "nxp,mcux-i2s";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#pinmux-cells = <2>;
|
|
reg = <0x40c40000 0x4000>;
|
|
clocks = <&ccm IMX_CCM_SAI4_CLK 0x2184 6>;
|
|
/* Source from audio PLL */
|
|
clock-mux = <6>;
|
|
pre-div = <0>;
|
|
podf = <63>;
|
|
pll-clocks = <&anatop 0 0 0>,
|
|
<&anatop 0 0 30>,
|
|
<&anatop 0 0 1>,
|
|
<&anatop 0 0 77>,
|
|
<&anatop 0 0 100>;
|
|
pll-clock-names = "src", "lp", "pd", "num", "den";
|
|
pinmuxes = <&iomuxcgpr 0x8 0x200>;
|
|
interrupts = <80 0>, <81 0>;
|
|
nxp,tx-channel = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
src: reset-controller@40c04000 {
|
|
compatible = "nxp,imx-src-rev2";
|
|
reg = <0x40c04000 0x4000>;
|
|
status = "okay";
|
|
};
|
|
|
|
|
|
qdec1: qdec@40174000 {
|
|
compatible = "nxp,mcux-qdec";
|
|
reg = <0x40174000 0x4000>;
|
|
interrupts = <165 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qdec2: qdec@40178000 {
|
|
compatible = "nxp,mcux-qdec";
|
|
reg = <0x40178000 0x4000>;
|
|
interrupts = <166 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qdec3: qdec@4017c000 {
|
|
compatible = "nxp,mcux-qdec";
|
|
reg = <0x4017c000 0x4000>;
|
|
interrupts = <167 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qdec4: qdec@40180000 {
|
|
compatible = "nxp,mcux-qdec";
|
|
reg = <0x40180000 0x4000>;
|
|
interrupts = <168 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
xbar1: xbar1@4003c000 {
|
|
compatible = "nxp,mcux-xbar";
|
|
reg = <0x4003c000 0x4000>;
|
|
interrupts = <143 0>, <144 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
xbar2: xbar2@40040000 {
|
|
compatible = "nxp,mcux-xbar";
|
|
reg = <0x40040000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
xbar3: xbar3@40044000 {
|
|
compatible = "nxp,mcux-xbar";
|
|
reg = <0x40044000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pit1: pit@400d8000 {
|
|
compatible = "nxp,pit";
|
|
reg = <0x400d8000 0x4000>;
|
|
clocks = <&ccm IMX_CCM_PIT_CLK 0x0 0>;
|
|
interrupts = <155 0>;
|
|
max-load-value = <0xffffffff>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pit1_channel0: pit1_channel@0 {
|
|
compatible = "nxp,pit-channel";
|
|
reg = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pit1_channel1: pit1_channel@1 {
|
|
compatible = "nxp,pit-channel";
|
|
reg = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pit1_channel2: pit1_channel@2 {
|
|
compatible = "nxp,pit-channel";
|
|
reg = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pit1_channel3: pit1_channel@3 {
|
|
compatible = "nxp,pit-channel";
|
|
reg = <3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pit2: pit@40cb0000 {
|
|
compatible = "nxp,pit";
|
|
reg = <0x40cb0000 0x4000>;
|
|
clocks = <&ccm IMX_CCM_PIT1_CLK 0x0 0>;
|
|
interrupts = <156 0>;
|
|
max-load-value = <0xffffffff>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pit2_channel0: pit2_channel@0 {
|
|
compatible = "nxp,pit-channel";
|
|
reg = <0>;
|
|
status = "disabled";
|
|
};
|
|
pit2_channel1: pit2_channel@1 {
|
|
compatible = "nxp,pit-channel";
|
|
reg = <1>;
|
|
status = "disabled";
|
|
};
|
|
pit2_channel2: pit2_channel@2 {
|
|
compatible = "nxp,pit-channel";
|
|
reg = <2>;
|
|
status = "disabled";
|
|
};
|
|
pit2_channel3: pit2_channel@3 {
|
|
compatible = "nxp,pit-channel";
|
|
reg = <3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <4>;
|
|
};
|
|
|
|
&systick {
|
|
/*
|
|
* RT11xx relies by default on the GPT Timer for system clock
|
|
* implementation, so the SysTick node should not be enabled.
|
|
*/
|
|
status = "disabled";
|
|
};
|