461 lines
9.5 KiB
Plaintext
461 lines
9.5 KiB
Plaintext
/*
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* Copyright (c) 2020, Linaro Ltd.
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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#include <arm/armv8-m.dtsi>
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/ {
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aliases {
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watchdog0 = &wwdt0;
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};
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chosen {
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zephyr,flash-controller = &iap;
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpu-power-states = <&sleep>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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cpu@1 {
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compatible = "arm,cortex-m33";
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reg = <1>;
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};
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power-states {
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sleep: sleep {
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compatible = "zephyr,power-state";
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power-state-name = "runtime-idle";
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min-residency-us = <4>;
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exit-latency-us = <4>;
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};
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};
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};
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};
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&sram {
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#address-cells = <1>;
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#size-cells = <1>;
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sramx: memory@4000000 {
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compatible = "mmio-sram";
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reg = <0x4000000 DT_SIZE_K(32)>;
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};
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/* lpc55S6x Memory configurations:
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*
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* RAM blocks SRAM0 through SRAM4 are contiguous address ranges
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*
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* LPC55S66: 144KB RAM, RAMX: 32K, SRAM0: 32K
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* LPC55S69: 320KB RAM, RAMX: 32K, SRAM0: 64K, SRAM1: 64K,
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* SRAM2: 64K, SRAM3: 64K, SRAM4: 16K
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*/
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(64)>;
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};
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sram1: memory@20010000 {
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compatible = "mmio-sram";
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reg = <0x20010000 DT_SIZE_K(64)>;
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};
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sram2: memory@20020000 {
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compatible = "mmio-sram";
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reg = <0x20020000 DT_SIZE_K(64)>;
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};
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sram3: memory@20030000 {
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compatible = "mmio-sram";
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reg = <0x20030000 DT_SIZE_K(64)>;
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};
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sram4: memory@20040000 {
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compatible = "mmio-sram";
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reg = <0x20040000 DT_SIZE_K(16)>;
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};
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};
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&peripheral {
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#address-cells = <1>;
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#size-cells = <1>;
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usb_sram: memory@100000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x100000 DT_SIZE_K(16)>;
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zephyr,memory-region = "USB_SRAM";
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zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
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};
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syscon: syscon@0 {
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compatible = "nxp,lpc-syscon";
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reg = <0x0 0x1000>;
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#clock-cells = <1>;
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};
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iap: flash-controller@34000 {
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compatible = "nxp,iap-fmc55";
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reg = <0x34000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0x0 DT_SIZE_K(630)>;
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erase-block-size = <512>;
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write-block-size = <512>;
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};
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flash_reserved: flash@9D800 {
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compatible = "soc-nv-flash";
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reg = <0x9D800 DT_SIZE_K(9)>;
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status = "disabled";
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};
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uuid: flash@9fc70 {
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compatible = "nxp,lpc-uid";
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reg = <0x9fc70 0x10>;
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};
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boot_rom: flash@3000000 {
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compatible = "soc-nv-flash";
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reg = <0x3000000 DT_SIZE_K(128)>;
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};
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};
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iocon: iocon@1000 {
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compatible = "nxp,lpc-iocon";
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reg = <0x1000 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1000 0x100>;
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pinctrl: pinctrl {
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compatible = "nxp,lpc-iocon-pinctrl";
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};
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};
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gpio0: gpio@0 {
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compatible = "nxp,lpc-gpio";
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reg = <0x8c000 0x2488>;
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int-source = "pint";
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gpio-controller;
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#gpio-cells = <2>;
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port = <0>;
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};
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gpio1: gpio@1 {
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compatible = "nxp,lpc-gpio";
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reg = <0x8c000 0x2488>;
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int-source = "pint";
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gpio-controller;
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#gpio-cells = <2>;
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port = <1>;
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};
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pint: pint@4000 {
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compatible = "nxp,pint";
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reg = <0x4000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
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<32 2>, <33 2>, <34 2>, <35 2>;
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num-lines = <8>;
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num-inputs = <64>;
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};
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dma0: dma-controller@82000 {
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compatible = "nxp,lpc-dma";
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reg = <0x82000 0x1000>;
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interrupts = <1 0>;
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dma-channels = <23>;
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nxp,dma-num-of-otrigs = <4>;
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nxp,dma-otrig-base-address = <LPC55S69_DMA0_OTRIG_BASE>;
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nxp,dma-itrig-base-address = <LPC55S69_DMA0_ITRIG_BASE>;
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status = "disabled";
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#dma-cells = <1>;
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};
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dma1: dma-controller@a7000 {
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compatible = "nxp,lpc-dma";
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reg = <0xa7000 0x1000>;
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interrupts = <58 0>;
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dma-channels = <10>;
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nxp,dma-num-of-otrigs = <4>;
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nxp,dma-otrig-base-address = <LPC55S69_DMA1_OTRIG_BASE>;
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nxp,dma-itrig-base-address = <LPC55S69_DMA1_ITRIG_BASE>;
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status = "disabled";
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#dma-cells = <1>;
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};
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mailbox0:mailbox@8b000 {
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compatible = "nxp,lpc-mailbox";
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reg = <0x8b000 0xEC>;
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interrupts = <31 0>;
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status = "disabled";
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};
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flexcomm0: flexcomm@86000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x86000 0x1000>;
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interrupts = <14 0>;
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clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
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status = "disabled";
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};
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flexcomm1: flexcomm@87000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x87000 0x1000>;
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interrupts = <15 0>;
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clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
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status = "disabled";
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};
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flexcomm2: flexcomm@88000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x88000 0x1000>;
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interrupts = <16 0>;
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clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
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status = "disabled";
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};
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flexcomm3: flexcomm@89000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x89000 0x1000>;
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interrupts = <17 0>;
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clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
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status = "disabled";
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};
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flexcomm4: flexcomm@8a000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x8a000 0x1000>;
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interrupts = <18 0>;
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clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
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status = "disabled";
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};
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flexcomm5: flexcomm@96000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x96000 0x1000>;
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interrupts = <19 0>;
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clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
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status = "disabled";
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};
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flexcomm6: flexcomm@97000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x97000 0x1000>;
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interrupts = <20 0>;
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clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
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status = "disabled";
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};
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flexcomm7: flexcomm@98000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x98000 0x1000>;
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interrupts = <21 0>;
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clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
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status = "disabled";
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};
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sdif: sdif@9b000 {
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compatible = "nxp,lpc-sdif";
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reg = <0x9b000 0x1000>;
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interrupts = <42 0>;
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clocks = <&syscon MCUX_SDIF_CLK>;
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status = "disabled";
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};
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hs_lspi: spi@9f000 {
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compatible = "nxp,lpc-spi";
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/* Enabling cs-gpios below will allow using GPIO CS,
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rather than Flexcomm SS */
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/* cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
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<&gpio1 1 GPIO_ACTIVE_LOW>,
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<&gpio1 12 GPIO_ACTIVE_LOW>,
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<&gpio1 26 GPIO_ACTIVE_LOW>; */
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reg = <0x9f000 0x1000>;
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interrupts = <59 0>;
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clocks = <&syscon MCUX_HS_SPI_CLK>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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rng: rng@3a000 {
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compatible = "nxp,lpc-rng";
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reg = <0x3a000 0x1000>;
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status = "okay";
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};
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wwdt0: watchdog@c000 {
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compatible = "nxp,lpc-wwdt";
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reg = <0xc000 0x1000>;
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interrupts = <0 0>;
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status = "disabled";
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clk-divider = <1>;
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};
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adc0: adc@A0000 {
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compatible = "nxp,lpc-lpadc";
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reg = <0xA0000 0x1000>;
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interrupts = <22 0>;
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status = "disabled";
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clk-divider = <8>;
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clk-source = <0>;
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voltage-ref= <1>;
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calibration-average = <128>;
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power-level = <0>;
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offset-value-a = <10>;
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offset-value-b = <10>;
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#io-channel-cells = <1>;
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clocks = <&syscon MCUX_LPADC1_CLK>;
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};
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usbfs: usbfs@84000 {
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compatible = "nxp,lpcip3511";
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reg = <0x84000 0x1000>;
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interrupts = <28 1>;
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num-bidir-endpoints = <5>;
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maximum-speed = "full-speed";
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status = "disabled";
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};
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usbhs: usbhs@94000 {
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compatible = "nxp,lpcip3511";
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reg = <0x94000 0x1000>;
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interrupts = <47 1>;
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num-bidir-endpoints = <6>;
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status = "disabled";
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};
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ctimer0: ctimer@8000 {
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compatible = "nxp,lpc-ctimer";
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reg = <0x8000 0x1000>;
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interrupts = <10 0>;
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status = "disabled";
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clk-source = <3>;
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clocks = <&syscon MCUX_CTIMER0_CLK>;
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mode = <0>;
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input = <0>;
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prescale = <0>;
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};
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ctimer1: ctimer@9000 {
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compatible = "nxp,lpc-ctimer";
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reg = <0x9000 0x1000>;
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interrupts = <11 0>;
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status = "disabled";
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clk-source = <3>;
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clocks = <&syscon MCUX_CTIMER1_CLK>;
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mode = <0>;
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input = <0>;
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prescale = <0>;
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};
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ctimer2: ctimer@28000 {
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compatible = "nxp,lpc-ctimer";
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reg = <0x28000 0x1000>;
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interrupts = <36 0>;
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status = "disabled";
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clk-source = <3>;
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clocks = <&syscon MCUX_CTIMER2_CLK>;
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mode = <0>;
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input = <0>;
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prescale = <0>;
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};
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ctimer3: ctimer@29000 {
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compatible = "nxp,lpc-ctimer";
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reg = <0x29000 0x1000>;
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interrupts = <13 0>;
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status = "disabled";
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clk-source = <3>;
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clocks = <&syscon MCUX_CTIMER3_CLK>;
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mode = <0>;
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input = <0>;
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prescale = <0>;
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};
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ctimer4: ctimer@2A000 {
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compatible = "nxp,lpc-ctimer";
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reg = <0x2A000 0x1000>;
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interrupts = <37 0>;
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status = "disabled";
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clk-source = <3>;
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clocks = <&syscon MCUX_CTIMER4_CLK>;
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mode = <0>;
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input = <0>;
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prescale = <0>;
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};
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sc_timer: pwm@85000 {
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compatible = "nxp,sctimer-pwm";
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reg = <0x85000 0x1000>;
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interrupts = <12 0>;
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status = "disabled";
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clocks = <&syscon MCUX_SCTIMER_CLK>;
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prescaler = <2>;
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#pwm-cells = <3>;
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};
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mrt: mrt@d000 {
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compatible = "nxp,mrt";
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reg = <0xd000 0x100>;
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interrupts = <9 0>;
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num-channels = <4>;
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num-bits = <24>;
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clocks = <&syscon MCUX_MRT_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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mrt_channel0: mrt_channel@0 {
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compatible = "nxp,mrt-channel";
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reg = <0>;
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status = "disabled";
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};
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mrt_channel1: mrt_channel@1 {
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compatible = "nxp,mrt-channel";
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reg = <1>;
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status = "disabled";
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};
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mrt_channel2: mrt_channel@2 {
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compatible = "nxp,mrt-channel";
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reg = <2>;
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status = "disabled";
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};
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mrt_channel3: mrt_channel@3 {
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compatible = "nxp,mrt-channel";
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reg = <3>;
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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