182 lines
6.3 KiB
C
182 lines
6.3 KiB
C
/*
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* Copyright (c) 2016-2017 Piotr Mienkowski
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief Atmel SAM MCU family General Purpose Input Output (GPIO)
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* module HAL driver.
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*/
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#ifndef _ATMEL_SAM_SOC_GPIO_H_
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#define _ATMEL_SAM_SOC_GPIO_H_
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#include <zephyr/types.h>
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#include <soc.h>
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#include <gpio.h>
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/*
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* Pin flags/attributes
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*/
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/* TODO: replace hard coded pin attribute values with defines provided
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* in gpio.h, once the official API is clean.
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*/
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#define SOC_GPIO_DEFAULT (0)
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#define SOC_GPIO_PULLUP (1 << 0)
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#define SOC_GPIO_PULLDOWN (1 << 1)
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#define SOC_GPIO_OPENDRAIN (1 << 2)
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/* Bit field: SOC_GPIO_IN_FILTER */
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#define SOC_GPIO_IN_FILTER_POS 3
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#define SOC_GPIO_IN_FILTER_MASK (3 << SOC_GPIO_IN_FILTER_POS)
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#define SOC_GPIO_IN_FILTER_NONE (0 << SOC_GPIO_IN_FILTER_POS)
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#define SOC_GPIO_IN_FILTER_DEBOUNCE (1 << SOC_GPIO_IN_FILTER_POS)
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#define SOC_GPIO_IN_FILTER_DEGLITCH (2 << SOC_GPIO_IN_FILTER_POS)
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#define SOC_GPIO_INT_ENABLE (1 << 5)
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/* Bit field: SOC_GPIO_INT_TRIG */
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#define SOC_GPIO_INT_TRIG_POS 6
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#define SOC_GPIO_INT_TRIG_MASK (3 << SOC_GPIO_INT_TRIG_POS)
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/** Interrupt is triggered by a level detection event. */
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#define SOC_GPIO_INT_TRIG_LEVEL (0 << SOC_GPIO_INT_TRIG_POS)
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/** Interrupt is triggered by an edge detection event. */
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#define SOC_GPIO_INT_TRIG_EDGE (1 << SOC_GPIO_INT_TRIG_POS)
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/** Interrupt is triggered by any edge detection event. */
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#define SOC_GPIO_INT_TRIG_DOUBLE_EDGE (2 << SOC_GPIO_INT_TRIG_POS)
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/** Interrupt is triggered by a high level / rising edge detection event */
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#define SOC_GPIO_INT_ACTIVE_HIGH (1 << 8)
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/* Bit field: SOC_GPIO_FUNC */
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#define SOC_GPIO_FUNC_POS 16
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#define SOC_GPIO_FUNC_MASK (7 << SOC_GPIO_FUNC_POS)
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/** Connect pin to peripheral A. */
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#define SOC_GPIO_FUNC_A (0 << SOC_GPIO_FUNC_POS)
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/** Connect pin to peripheral B. */
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#define SOC_GPIO_FUNC_B (1 << SOC_GPIO_FUNC_POS)
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/** Connect pin to peripheral C. */
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#define SOC_GPIO_FUNC_C (2 << SOC_GPIO_FUNC_POS)
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/** Connect pin to peripheral D. */
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#define SOC_GPIO_FUNC_D (3 << SOC_GPIO_FUNC_POS)
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/** Configure pin as input. */
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#define SOC_GPIO_FUNC_IN (4 << SOC_GPIO_FUNC_POS)
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/** Configure pin as output and set it initial value to 0. */
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#define SOC_GPIO_FUNC_OUT_0 (5 << SOC_GPIO_FUNC_POS)
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/** Configure pin as output and set it initial value to 1. */
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#define SOC_GPIO_FUNC_OUT_1 (6 << SOC_GPIO_FUNC_POS)
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struct soc_gpio_pin {
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u32_t mask; /** pin(s) bit mask */
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Pio *regs; /** pointer to registers of the PIO controller */
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u8_t periph_id; /** peripheral ID of the PIO controller */
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u32_t flags; /** pin flags/attributes */
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};
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/**
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* @brief Configure GPIO pin(s).
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*
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* Configure one or several pins belonging to the same GPIO port.
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* Example scenarios:
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* - configure pin(s) as input with debounce filter enabled.
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* - connect pin(s) to a peripheral B and enable pull-up.
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* - configure pin(s) as open drain output.
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* All pins are configured in the same way.
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*
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* @remark The function will enable the GPIO module's clock only if
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* any of its pins is configured as an input. This is typically what
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* a user wants. A pin will function correctly without clock enabled
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* when configured as an output or connected to a peripheral.
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* In some cases, e.g. when a pin is configured as an output with
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* a pull-up and user wants to read pin's input value it is necessary
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* to enable GPIO module's clock separately.
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*
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* @param pin pin's configuration data such as pin mask, pin attributes, etc.
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*/
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void soc_gpio_configure(const struct soc_gpio_pin *pin);
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/**
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* @brief Configure a list of GPIO pin(s).
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*
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* Configure an arbitrary amount of pins in an arbitrary way. Each
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* configuration entry is a single item in an array passed as an
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* argument to the function.
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*
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* @param pins an array where each item contains pin's configuration data.
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* @param size size of the pin list.
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*/
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void soc_gpio_list_configure(const struct soc_gpio_pin pins[],
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unsigned int size);
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/**
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* @brief Set pin(s) high.
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*
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* Set pin(s) defined in the mask parameter to high. The pin(s) have to be
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* configured as output by the configure function. The flags field which
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* is part of pin struct is ignored.
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*
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* @param pin pointer to a pin instance describing one or more pins.
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*/
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static inline void soc_gpio_set(const struct soc_gpio_pin *pin)
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{
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pin->regs->PIO_SODR = pin->mask;
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}
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/**
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* @brief Set pin(s) low.
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*
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* Set pin(s) defined in the mask field to low. The pin(s) have to be
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* configured as output by the configure function. The flags field which
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* is part of pin struct is ignored.
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*
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* @param pin pointer to a pin instance describing one or more pins.
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*/
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static inline void soc_gpio_clear(const struct soc_gpio_pin *pin)
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{
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pin->regs->PIO_CODR = pin->mask;
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}
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/**
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* @brief Get pin(s) value.
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*
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* Get value of the pin(s) defined in the mask field.
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*
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* @param pin pointer to a pin instance describing one or more pins.
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* @return pin(s) value. To assess value of a specific pin the pin's bit
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* field has to be read.
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*/
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static inline u32_t soc_gpio_get(const struct soc_gpio_pin *pin)
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{
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return pin->regs->PIO_PDSR & pin->mask;
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}
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/**
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* @brief Set the length of the debounce window.
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*
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* The debouncing filter automatically rejects a pulse with a duration of less
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* than 1/2 programmable divided slow clock period tdiv_slck, while a pulse with
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* a duration of one or more tdiv_slck cycles is accepted. For pulse durations
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* between 1/2 selected clock cycle and one tdiv_slck clock cycle, the pulse may
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* or may not be taken into account, depending on the precise timing of its
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* occurrence.
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*
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* tdiv_slck = ((div + 1) x 2) x tslck
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* where tslck is the slow clock, typically 32.768 kHz.
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*
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* Setting the length of the debounce window is only meaningful if the pin is
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* configured as input and the debounce pin option is enabled.
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*
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* @param pin pointer to a pin instance describing one or more pins.
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* @param div slow clock divider, valid values: from 0 to 2^14 - 1
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*/
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static inline void soc_gpio_debounce_length_set(const struct soc_gpio_pin *pin,
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u32_t div)
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{
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pin->regs->PIO_SCDR = PIO_SCDR_DIV(div);
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}
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#endif /* _ATMEL_SAM_SOC_GPIO_H_ */
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