44 lines
1.1 KiB
C
44 lines
1.1 KiB
C
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM Cortex-M interrupt initialization
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*
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* The ARM Cortex-M architecture provides its own k_thread_abort() to deal with
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* different CPU modes (handler vs thread) when a thread aborts. When its entry
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* point returns or when it aborts itself, the CPU is in thread mode and must
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* call _Swap() (which triggers a service call), but when in handler mode, the
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* CPU must exit handler mode to cause the context switch, and thus must queue
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* the PendSV exception.
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <arch/arm/cortex_m/cmsis.h>
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/**
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*
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* @brief Initialize interrupts
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*
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* Ensures all interrupts have their priority set to _EXC_IRQ_DEFAULT_PRIO and
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* not 0, which they have it set to when coming out of reset. This ensures that
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* interrupt locking via BASEPRI works as expected.
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*
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* @return N/A
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*/
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void _IntLibInit(void)
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{
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int irq = 0;
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for (; irq < CONFIG_NUM_IRQS; irq++) {
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NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
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}
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}
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