170 lines
3.9 KiB
C
170 lines
3.9 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief ARM CORTEX-M3 interrupt management
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*
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*
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* Interrupt management: enabling/disabling and dynamic ISR
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* connecting/replacing. SW_ISR_TABLE_DYNAMIC has to be enabled for
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* connecting ISRs at runtime.
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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#include <misc/__assert.h>
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#include <toolchain.h>
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#include <sections.h>
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#include <sw_isr_table.h>
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extern void __reserved(void);
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/**
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*
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* @brief Enable an interrupt line
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*
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* Clear possible pending interrupts on the line, and enable the interrupt
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* line. After this call, the CPU will receive interrupts for the specified
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* <irq>.
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*
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* @return N/A
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*/
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void irq_enable(unsigned int irq)
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{
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/* before enabling interrupts, ensure that interrupt is cleared */
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_NvicIrqUnpend(irq);
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_NvicIrqEnable(irq);
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}
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/**
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*
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* @brief Disable an interrupt line
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*
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* Disable an interrupt line. After this call, the CPU will stop receiving
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* interrupts for the specified <irq>.
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*
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* @return N/A
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*/
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void irq_disable(unsigned int irq)
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{
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_NvicIrqDisable(irq);
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}
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/**
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* @internal
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*
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* @brief Set an interrupt's priority
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*
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* Valid values are from 1 to 255. Interrupts of priority 1 are not masked when
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* interrupts are locked system-wide, so care must be taken when using them. ISR
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* installed with priority 1 interrupts cannot make kernel calls.
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*
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* Priority 0 is reserved for kernel usage and cannot be used.
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*
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* The priority is verified if ASSERT_ON is enabled.
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*
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* @return N/A
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*/
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void _irq_priority_set(unsigned int irq,
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unsigned int prio)
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{
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__ASSERT(prio > 0 && prio < 256, "invalid priority!");
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_NvicIrqPrioSet(irq, _EXC_PRIO(prio));
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}
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/**
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*
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* @brief Spurious interrupt handler
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*
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* Installed in all dynamic interrupt slots at boot time. Throws an error if
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* called.
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*
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* See __reserved().
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*
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* @return N/A
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*/
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void _irq_spurious(void *unused)
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{
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ARG_UNUSED(unused);
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__reserved();
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}
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#if CONFIG_SW_ISR_TABLE_DYNAMIC
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/**
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* @internal
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*
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* @brief Replace an interrupt handler by another
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*
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* An interrupt's ISR can be replaced at runtime.
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*
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* @return N/A
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*/
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void _irq_handler_set(unsigned int irq,
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void (*new)(void *arg),
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void *arg)
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{
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int key = irq_lock();
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_sw_isr_table[irq].isr = new;
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_sw_isr_table[irq].arg = arg;
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irq_unlock(key);
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}
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/**
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*
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* @brief Connect an ISR to an interrupt line
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*
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* <isr> is connected to interrupt line <irq> (exception #<irq>+16). No prior
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* ISR can have been connected on <irq> interrupt line since the system booted.
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*
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* This routine will hang if another ISR was connected for interrupt line <irq>
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* and ASSERT_ON is enabled; if ASSERT_ON is disabled, it will fail silently.
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*
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* @return the interrupt line number
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*/
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int irq_connect_dynamic(unsigned int irq,
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unsigned int prio,
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void (*isr)(void *arg),
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void *arg,
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uint32_t flags)
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{
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ARG_UNUSED(flags);
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_irq_handler_set(irq, isr, arg);
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_irq_priority_set(irq, prio);
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return irq;
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}
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/**
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*
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* @internal
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*
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* @brief Disconnect an ISR from an interrupt line
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*
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* Interrupt line <irq> (exception #<irq>+16) is disconnected from its ISR and
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* the latter is replaced by _irq_spurious(). irq_disable() should have
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* been called before invoking this routine.
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*
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* @return N/A
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*/
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void _irq_disconnect(unsigned int irq)
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{
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_irq_handler_set(irq, _irq_spurious, NULL);
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}
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#endif /* CONFIG_SW_ISR_TABLE_DYNAMIC */
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