336 lines
8.3 KiB
C
336 lines
8.3 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <soc.h>
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#include <gpio.h>
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#include <clock_control/stm32_clock_control.h>
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#include <pinmux/stm32/pinmux_stm32.h>
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#include <pinmux.h>
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#include <gpio/gpio_stm32.h>
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#include <misc/util.h>
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#include <interrupt_controller/exti_stm32.h>
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#include "gpio_utils.h"
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/**
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* @brief Common GPIO driver for STM32 MCUs. Each SoC must implement a
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* SoC specific integration glue
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*/
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/**
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* @brief EXTI interrupt callback
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*/
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static void gpio_stm32_isr(int line, void *arg)
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{
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struct device *dev = arg;
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struct gpio_stm32_data *data = dev->driver_data;
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if (BIT(line) & data->cb_pins) {
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_gpio_fire_callbacks(&data->cb, dev, BIT(line));
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}
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}
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/**
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* @brief Configure pin or port
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*/
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static int gpio_stm32_config(struct device *dev, int access_op,
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uint32_t pin, int flags)
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{
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const struct gpio_stm32_config *cfg = dev->config->config_info;
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int pincfg;
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int map_res;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENODEV;
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}
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/* figure out if we can map the requested GPIO
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* configuration
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*/
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map_res = stm32_gpio_flags_to_conf(flags, &pincfg);
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if (map_res) {
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return map_res;
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}
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if (stm32_gpio_configure(cfg->base, pin, pincfg, 0)) {
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return -EIO;
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}
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if (flags & GPIO_INT) {
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stm32_exti_set_callback(pin, gpio_stm32_isr, dev);
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stm32_gpio_enable_int(cfg->port, pin);
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if (flags & GPIO_INT_EDGE) {
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int edge = 0;
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if (flags & GPIO_INT_DOUBLE_EDGE) {
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edge = STM32_EXTI_TRIG_RISING |
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STM32_EXTI_TRIG_FALLING;
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} else if (flags & GPIO_INT_ACTIVE_HIGH) {
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edge = STM32_EXTI_TRIG_RISING;
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} else {
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edge = STM32_EXTI_TRIG_FALLING;
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}
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stm32_exti_trigger(pin, edge);
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}
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stm32_exti_enable(pin);
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}
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return 0;
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}
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/**
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* @brief Set the pin or port output
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*/
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static int gpio_stm32_write(struct device *dev, int access_op,
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uint32_t pin, uint32_t value)
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{
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const struct gpio_stm32_config *cfg = dev->config->config_info;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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return stm32_gpio_set(cfg->base, pin, value);
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}
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/**
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* @brief Read the pin or port status
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*/
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static int gpio_stm32_read(struct device *dev, int access_op,
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uint32_t pin, uint32_t *value)
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{
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const struct gpio_stm32_config *cfg = dev->config->config_info;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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*value = stm32_gpio_get(cfg->base, pin);
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return 0;
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}
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static int gpio_stm32_manage_callback(struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_stm32_data *data = dev->driver_data;
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_gpio_manage_callback(&data->cb, callback, set);
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return 0;
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}
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static int gpio_stm32_enable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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struct gpio_stm32_data *data = dev->driver_data;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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data->cb_pins |= BIT(pin);
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return 0;
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}
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static int gpio_stm32_disable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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struct gpio_stm32_data *data = dev->driver_data;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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data->cb_pins &= ~BIT(pin);
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return 0;
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}
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static const struct gpio_driver_api gpio_stm32_driver = {
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.config = gpio_stm32_config,
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.write = gpio_stm32_write,
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.read = gpio_stm32_read,
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.manage_callback = gpio_stm32_manage_callback,
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.enable_callback = gpio_stm32_enable_callback,
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.disable_callback = gpio_stm32_disable_callback,
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};
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/**
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* @brief Initialize GPIO port
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*
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* Perform basic initialization of a GPIO port. The code will
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* enable the clock for corresponding peripheral.
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*
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* @param dev GPIO device struct
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*
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* @return 0
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*/
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static int gpio_stm32_init(struct device *device)
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{
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const struct gpio_stm32_config *cfg = device->config->config_info;
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/* enable clock for subsystem */
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struct device *clk =
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device_get_binding(STM32_CLOCK_CONTROL_NAME);
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#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32L4X)
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clock_control_on(clk, cfg->clock_subsys);
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#elif CONFIG_SOC_SERIES_STM32F4X
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clock_control_on(clk, (clock_control_subsys_t *) &cfg->pclken);
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#endif
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return 0;
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}
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#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32L4X)
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/* TODO: Change F1 to work similarly to F4 */
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#define GPIO_DEVICE_INIT(__name, __suffix, __base_addr, __port, __clock) \
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static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \
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.base = (uint32_t *)__base_addr, \
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.port = __port, \
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.clock_subsys = UINT_TO_POINTER(__clock), \
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}; \
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static struct gpio_stm32_data gpio_stm32_data_## __suffix; \
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DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \
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__name, \
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gpio_stm32_init, \
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&gpio_stm32_data_## __suffix, \
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&gpio_stm32_cfg_## __suffix, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&gpio_stm32_driver);
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#elif CONFIG_SOC_SERIES_STM32F4X
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#define GPIO_DEVICE_INIT(__name, __suffix, __base_addr, __port, __cenr) \
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static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \
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.base = (uint32_t *)__base_addr, \
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.port = __port, \
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.pclken = { .bus = STM32F4X_CLOCK_BUS_AHB1, .enr = __cenr }, \
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}; \
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static struct gpio_stm32_data gpio_stm32_data_## __suffix; \
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DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \
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__name, \
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gpio_stm32_init, \
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&gpio_stm32_data_## __suffix, \
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&gpio_stm32_cfg_## __suffix, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&gpio_stm32_driver);
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#endif
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#ifdef CONFIG_GPIO_STM32_PORTA
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GPIO_DEVICE_INIT("GPIOA", a, GPIOA_BASE, STM32_PORTA,
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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STM32F10X_CLOCK_SUBSYS_IOPA
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| STM32F10X_CLOCK_SUBSYS_AFIO
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#elif CONFIG_SOC_SERIES_STM32F4X
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STM32F4X_CLOCK_ENABLE_GPIOA
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#elif defined(CONFIG_SOC_SERIES_STM32L4X)
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STM32L4X_CLOCK_SUBSYS_GPIOA
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#endif
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);
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#endif /* CONFIG_GPIO_STM32_PORTA */
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#ifdef CONFIG_GPIO_STM32_PORTB
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GPIO_DEVICE_INIT("GPIOB", b, GPIOB_BASE, STM32_PORTB,
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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STM32F10X_CLOCK_SUBSYS_IOPB
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| STM32F10X_CLOCK_SUBSYS_AFIO
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#elif CONFIG_SOC_SERIES_STM32F4X
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STM32F4X_CLOCK_ENABLE_GPIOB
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#elif defined(CONFIG_SOC_SERIES_STM32L4X)
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STM32L4X_CLOCK_SUBSYS_GPIOB
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#endif
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);
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#endif /* CONFIG_GPIO_STM32_PORTB */
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#ifdef CONFIG_GPIO_STM32_PORTC
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GPIO_DEVICE_INIT("GPIOC", c, GPIOC_BASE, STM32_PORTC,
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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STM32F10X_CLOCK_SUBSYS_IOPC
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| STM32F10X_CLOCK_SUBSYS_AFIO
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#elif CONFIG_SOC_SERIES_STM32F4X
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STM32F4X_CLOCK_ENABLE_GPIOC
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#elif defined(CONFIG_SOC_SERIES_STM32L4X)
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STM32L4X_CLOCK_SUBSYS_GPIOC
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#endif
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);
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#endif /* CONFIG_GPIO_STM32_PORTC */
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#ifdef CONFIG_GPIO_STM32_PORTD
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GPIO_DEVICE_INIT("GPIOD", d, GPIOD_BASE, STM32_PORTD,
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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STM32F10X_CLOCK_SUBSYS_IOPD
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| STM32F10X_CLOCK_SUBSYS_AFIO
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#elif CONFIG_SOC_SERIES_STM32F4X
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STM32F4X_CLOCK_ENABLE_GPIOD
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#elif defined(CONFIG_SOC_SERIES_STM32L4X)
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STM32L4X_CLOCK_SUBSYS_GPIOD
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#endif
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);
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#endif /* CONFIG_GPIO_STM32_PORTD */
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#ifdef CONFIG_GPIO_STM32_PORTE
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GPIO_DEVICE_INIT("GPIOE", e, GPIOE_BASE, STM32_PORTE,
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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STM32F10X_CLOCK_SUBSYS_IOPE
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| STM32F10X_CLOCK_SUBSYS_AFIO
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#elif CONFIG_SOC_SERIES_STM32F4X
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STM32F4X_CLOCK_ENABLE_GPIOE
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#elif defined(CONFIG_SOC_SERIES_STM32L4X)
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STM32L4X_CLOCK_SUBSYS_GPIOE
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#endif
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);
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#endif /* CONFIG_GPIO_STM32_PORTE */
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#ifdef CONFIG_GPIO_STM32_PORTF
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GPIO_DEVICE_INIT("GPIOF", f, GPIOF_BASE, STM32_PORTF,
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#if defined(CONFIG_SOC_SERIES_STM32L4X)
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STM32L4X_CLOCK_SUBSYS_GPIOF
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#endif
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);
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#endif /* CONFIG_GPIO_STM32_PORTF */
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#ifdef CONFIG_GPIO_STM32_PORTG
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GPIO_DEVICE_INIT("GPIOG", g, GPIOG_BASE, STM32_PORTG,
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#if defined(CONFIG_SOC_SERIES_STM32L4X)
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STM32L4X_CLOCK_SUBSYS_GPIOG
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#endif
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);
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#endif /* CONFIG_GPIO_STM32_PORTG */
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#ifdef CONFIG_GPIO_STM32_PORTH
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GPIO_DEVICE_INIT("GPIOH", h, GPIOH_BASE, STM32_PORTH,
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#if defined(CONFIG_SOC_SERIES_STM32L4X)
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STM32L4X_CLOCK_SUBSYS_GPIOH
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#endif
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);
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#endif /* CONFIG_GPIO_STM32_PORTH */
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