348 lines
8.8 KiB
C
348 lines
8.8 KiB
C
/*
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* Copyright (c) 2022 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ite_peci_it8xxx2
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/peci.h>
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#include <zephyr/kernel.h>
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/peci.h>
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#include <soc.h>
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#include <soc_dt.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/util.h>
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LOG_MODULE_REGISTER(peci_ite_it8xxx2, CONFIG_PECI_LOG_LEVEL);
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BUILD_ASSERT(IS_ENABLED(CONFIG_PECI_INTERRUPT_DRIVEN),
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"Please enable the option CONFIG_PECI_INTERRUPT_DRIVEN");
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/*
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* This driver is single-instance. If the devicetree contains multiple
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* instances, this will fail and the driver needs to be revisited.
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*/
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1,
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"Unsupported PECI Instance");
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/* The following constants describes the bitrate of it8xxx2 PECI,
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* for the frequency are 2000KHz, 1000KHz, and 1600KHz. (Unit: KHz)
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*/
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#define PECI_IT8XXX2_BITRATE_2MHZ 2000
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#define PECI_IT8XXX2_BITRATE_1MHZ 1000
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#define PECI_IT8XXX2_BITRATE_1P6MHZ 1600
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/* The following masks are designed for the PECI bitrate settings,
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* for the bits[7:3] are not related to this features.
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*/
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#define PECI_IT8XXX2_BITRATE_BITS_MASK 0x07
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#define PECI_IT8XXX2_BITRATE_2MHZ_BITS 0x00
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#define PECI_IT8XXX2_BITRATE_1MHZ_BITS 0x01
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#define PECI_IT8XXX2_BITRATE_1P6MHZ_BITS 0x04
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/* The Transaction Timeout */
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#define PECI_TIMEOUT_MS 30
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/* PECI interface 0 */
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#define PECI0 0
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/* HOSTAR (F02C00h) */
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#define HOBY BIT(0)
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#define FINISH BIT(1)
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#define RD_FCS_ERR BIT(2)
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#define WR_FCS_ERR BIT(3)
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#define EXTERR BIT(5)
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#define BUS_ER BIT(6)
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#define TEMPERR BIT(7)
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#define HOSTAR_RST_ANYBIT \
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(TEMPERR|BUS_ER|EXTERR|WR_FCS_ERR|RD_FCS_ERR|FINISH)
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/* HOCTLR (F02C01h) */
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#define START BIT(0)
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#define AWFCS_EN BIT(1)
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#define CONTROL BIT(2)
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#define PECIHEN BIT(3)
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#define FCSERR_ABT BIT(4)
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#define FIFOCLR BIT(5)
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/*
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* TODO: The Voltage Configuration
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* Related DTSi and registers settings should be fulfilled
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* in the future.
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*/
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/* PADCTLR (F02C0Eh) */
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#define PECI_DVIE 0x04
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enum peci_vtts {
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HOVTTS0P85V = 0x00,
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HOVTTS0P90V = 0x01,
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HOVTTS0P95V = 0x02,
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HOVTTS1P00V = 0x03,
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HOVTTS1P05V = 0x08,
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HOVTTS1P10V = 0x09,
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HOVTTS1P15V = 0x0A,
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HOVTTS1P20V = 0x0B,
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HOVTTS1P25V = 0x10,
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};
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struct peci_it8xxx2_config {
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uintptr_t base_addr;
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uint8_t irq_no;
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const struct pinctrl_dev_config *pcfg;
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};
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struct peci_it8xxx2_data {
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struct peci_msg *msgs;
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struct k_sem device_sync_sem;
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uint32_t bitrate;
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};
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PINCTRL_DT_INST_DEFINE(0);
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static const struct peci_it8xxx2_config peci_it8xxx2_config0 = {
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.base_addr = DT_INST_REG_ADDR(0),
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.irq_no = DT_INST_IRQN(0),
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
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};
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static struct peci_it8xxx2_data peci_it8xxx2_data0;
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/* ITE IT8XXX2 PECI Functions */
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static void peci_it8xxx2_init_vtts(struct peci_it8xxx2_regs *reg_base,
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enum peci_vtts vol_opt)
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{
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reg_base->PADCTLR = (reg_base->PADCTLR & PECI_DVIE) | vol_opt;
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}
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static void peci_it8xxx2_rst_status(struct peci_it8xxx2_regs *reg_base)
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{
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reg_base->HOSTAR = HOSTAR_RST_ANYBIT;
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}
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static int peci_it8xxx2_check_host_busy(struct peci_it8xxx2_regs *reg_base)
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{
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return (reg_base->HOSTAR & HOBY) ? (-EBUSY) : 0;
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}
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static int peci_it8xxx2_check_host_finish(const struct device *dev)
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{
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struct peci_it8xxx2_data *data = dev->data;
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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int ret = k_sem_take(&data->device_sync_sem, K_MSEC(PECI_TIMEOUT_MS));
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if (ret == -EAGAIN) {
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LOG_ERR("%s: Timeout", __func__);
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return -ETIMEDOUT;
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}
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if (peci_regs->HOSTAR != FINISH) {
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LOG_ERR("[PECI] Error: HOSTAR=0x%02X\r\n", peci_regs->HOSTAR);
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return -EIO;
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}
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return 0;
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}
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static int peci_it8xxx2_configure(const struct device *dev, uint32_t bitrate)
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{
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struct peci_it8xxx2_data *data = dev->data;
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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uint8_t hoctl2r_to_write;
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data->bitrate = bitrate;
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hoctl2r_to_write =
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(peci_regs->HOCTL2R) & (~(PECI_IT8XXX2_BITRATE_BITS_MASK));
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switch (bitrate) {
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case PECI_IT8XXX2_BITRATE_2MHZ:
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break;
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case PECI_IT8XXX2_BITRATE_1MHZ:
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hoctl2r_to_write |= PECI_IT8XXX2_BITRATE_1MHZ_BITS;
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break;
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case PECI_IT8XXX2_BITRATE_1P6MHZ:
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hoctl2r_to_write |= PECI_IT8XXX2_BITRATE_1P6MHZ_BITS;
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break;
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default:
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LOG_ERR("[PECI] Error: Specified Bitrate Not Supported\r\n");
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hoctl2r_to_write |= PECI_IT8XXX2_BITRATE_1MHZ_BITS;
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data->bitrate = PECI_IT8XXX2_BITRATE_1MHZ;
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peci_regs->HOCTL2R = hoctl2r_to_write;
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return -ENOTSUP;
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}
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peci_regs->HOCTL2R = hoctl2r_to_write;
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return 0;
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}
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static int peci_it8xxx2_enable(const struct device *dev)
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{
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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peci_regs->HOCTLR |= (FIFOCLR|FCSERR_ABT|PECIHEN|CONTROL);
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return 0;
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}
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static int peci_it8xxx2_disable(const struct device *dev)
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{
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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peci_regs->HOCTLR &= ~(PECIHEN);
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return 0;
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}
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static void peci_it8xxx2_rst_module(const struct device *dev)
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{
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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LOG_ERR("[PECI] Module Reset for Status Error.\r\n");
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/* Reset IT8XXX2 PECI Module Thoroughly */
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IT83XX_GCTRL_RSTC4 |= RPECI;
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/*
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* Due to the fact that we've checked if the peci_enable()
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* called before calling the peci_transfer(), so the peci
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* were definitely enabled before the error occurred.
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* Here is the recovery mechanism for recovering the PECI
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* bus when the errors occur.
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*/
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peci_regs->PADCTLR |= PECI_DVIE;
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peci_it8xxx2_init_vtts(peci_regs, HOVTTS0P95V);
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peci_it8xxx2_configure(dev, PECI_IT8XXX2_BITRATE_1MHZ);
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peci_it8xxx2_enable(dev);
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LOG_ERR("[PECI] Reinitialization Finished.\r\n");
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}
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static int peci_it8xxx2_transfer(const struct device *dev, struct peci_msg *msg)
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{
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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struct peci_buf *peci_rx_buf = &msg->rx_buffer;
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struct peci_buf *peci_tx_buf = &msg->tx_buffer;
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int cnt, ret_code;
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ret_code = 0;
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if (!(peci_regs->HOCTLR & PECIHEN)) {
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LOG_ERR("[PECI] Please call the peci_enable() first.\r\n");
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return -ECONNREFUSED;
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}
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if (peci_it8xxx2_check_host_busy(peci_regs) != 0) {
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return -EBUSY;
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}
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peci_regs->HOTRADDR = msg->addr;
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peci_regs->HOWRLR = peci_tx_buf->len;
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peci_regs->HORDLR = peci_rx_buf->len;
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peci_regs->HOCMDR = msg->cmd_code;
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if (msg->cmd_code != PECI_CMD_PING) {
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for (cnt = 0; cnt < (peci_tx_buf->len - 1); cnt++) {
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peci_regs->HOWRDR = peci_tx_buf->buf[cnt];
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}
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}
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/* Host Available */
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irq_enable(config->irq_no);
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peci_regs->HOCTLR |= START;
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ret_code = peci_it8xxx2_check_host_finish(dev);
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if (!ret_code) {
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/* Host Transactions Finished, Fetch Data from the regs */
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if (peci_rx_buf->len) {
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for (cnt = 0; cnt < (peci_rx_buf->len); cnt++) {
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peci_rx_buf->buf[cnt] = peci_regs->HORDDR;
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}
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}
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peci_it8xxx2_rst_status(peci_regs);
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} else {
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/* Host Transactions Failure */
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peci_it8xxx2_rst_module(dev);
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}
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return (ret_code);
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}
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static void peci_it8xxx2_isr(const struct device *dev)
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{
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struct peci_it8xxx2_data *data = dev->data;
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const struct peci_it8xxx2_config *config = dev->config;
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irq_disable(config->irq_no);
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k_sem_give(&data->device_sync_sem);
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}
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static const struct peci_driver_api peci_it8xxx2_driver_api = {
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.config = peci_it8xxx2_configure,
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.enable = peci_it8xxx2_enable,
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.disable = peci_it8xxx2_disable,
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.transfer = peci_it8xxx2_transfer,
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};
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static int peci_it8xxx2_init(const struct device *dev)
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{
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struct peci_it8xxx2_data *data = dev->data;
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const struct peci_it8xxx2_config *config = dev->config;
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struct peci_it8xxx2_regs *const peci_regs =
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(struct peci_it8xxx2_regs *)config->base_addr;
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int status;
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/* Initialize Semaphore */
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k_sem_init(&data->device_sync_sem, 0, 1);
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/* Configure the GPF6 to Alternative Function 3: PECI */
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status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (status < 0) {
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LOG_ERR("Failed to configure PECI pins");
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return status;
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}
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peci_regs->PADCTLR |= PECI_DVIE;
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peci_it8xxx2_init_vtts(peci_regs, HOVTTS0P95V);
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peci_it8xxx2_configure(dev, PECI_IT8XXX2_BITRATE_1MHZ);
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/* Interrupt Assignment */
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IRQ_CONNECT(DT_INST_IRQN(0),
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0,
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peci_it8xxx2_isr,
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DEVICE_DT_INST_GET(0),
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0);
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return 0;
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}
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DEVICE_DT_INST_DEFINE(0,
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&peci_it8xxx2_init,
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NULL,
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&peci_it8xxx2_data0,
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&peci_it8xxx2_config0,
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POST_KERNEL, CONFIG_PECI_INIT_PRIORITY,
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&peci_it8xxx2_driver_api);
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