9ed51516ed
This commit removes the enum array with allowed values for the `riscv,isa` field. There are many ways in which RISC-V ISA extension string can be represented, and listing them all is futile. In addition, custom extensions can be implemented, meaning every extension would have to be listed in the enum array as well. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com> |
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| .. | ||
| openisa,rv32m1-pcc.yaml | ||
| riscv,cpus.yaml | ||
| sifive,e24.yaml | ||
| sifive,e31.yaml | ||
| sifive,e51.yaml | ||
| sifive,s7.yaml | ||
| sifive-common.yaml | ||