Daniel Leung e444cc9fb9 xtensa: mmu: always map data TLB for VECBASE ... This adds code to always map data TLB for VECBASE so that we would be dealing with fewer data TLB misses during exception handling. With VECBASE always mapped, there is no need to pre-load anymore. Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2023-05-23 08:54:29 +02:00
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kernel_arch_func.h	xtensa: mmu: Initial implementation	2023-05-23 08:54:29 +02:00
offsets_short_arch.h	arch/xtensa: General cleanup, remove dead code	2021-03-08 11:14:27 -05:00
xtensa-asm2-context.h	xtensa: add some structs for interrupt stack frames	2023-04-20 04:45:52 -04:00
xtensa-asm2-s.h	xtensa: mmu: always map data TLB for VECBASE	2023-05-23 08:54:29 +02:00
xtensa-asm2.h	arch: migrate includes to <zephyr/...>	2022-05-06 19:57:22 +02:00