73 lines
1.2 KiB
Plaintext
73 lines
1.2 KiB
Plaintext
/*
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* Copyright (c) 2017 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/intel-ioapic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "qemu32";
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reg = <0>;
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};
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};
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intc: ioapic@fec00000 {
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compatible = "intel,ioapic";
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reg = <0xfec00000 0x100000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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flash0: flash@1000 {
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compatible = "soc-nv-flash";
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reg = <0x00001000 DT_FLASH_SIZE>;
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};
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sram0: memory@400000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x00400000 DT_SRAM_SIZE>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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uart0: uart@3f8 {
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compatible = "ns16550";
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reg = <0x000003f8 0x100>;
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label = "UART_0";
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clock-frequency = <1843200>;
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interrupts = <4 IRQ_TYPE_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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uart1: uart@2f8 {
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compatible = "ns16550";
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reg = <0x000002f8 0x100>;
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label = "UART_1";
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clock-frequency = <1843200>;
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interrupts = <3 IRQ_TYPE_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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};
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};
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