413 lines
10 KiB
C
413 lines
10 KiB
C
/*
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* Copyright (c) 2017 Piotr Mienkowski
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief I2C bus (TWIHS) driver for Atmel SAM MCU family.
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*
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* Only I2C Master Mode with 7 bit addressing is currently supported.
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*/
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#define SYS_LOG_DOMAIN "dev/i2c_sam_twihs"
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_I2C_LEVEL
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#include <logging/sys_log.h>
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#include <errno.h>
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#include <misc/__assert.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <i2c.h>
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#include "i2c-priv.h"
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/** I2C bus speed [Hz] in Standard Mode */
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#define BUS_SPEED_STANDARD_HZ 100000U
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/** I2C bus speed [Hz] in Fast Mode */
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#define BUS_SPEED_FAST_HZ 400000U
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/** I2C bus speed [Hz] in High Speed Mode */
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#define BUS_SPEED_HIGH_HZ 3400000U
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/* Maximum value of Clock Divider (CKDIV) */
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#define CKDIV_MAX 7
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/* Device constant configuration parameters */
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struct i2c_sam_twihs_dev_cfg {
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Twihs *regs;
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void (*irq_config)(void);
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u32_t bitrate;
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const struct soc_gpio_pin *pin_list;
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u8_t pin_list_size;
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u8_t periph_id;
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u8_t irq_id;
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};
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struct twihs_msg {
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/* Buffer containing data to read or write */
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u8_t *buf;
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/* Length of the buffer */
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u32_t len;
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/* Index of the next byte to be read/written from/to the buffer */
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u32_t idx;
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/* Value of TWIHS_SR at the end of the message */
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u32_t twihs_sr;
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/* Transfer flags as defined in the i2c.h file */
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u8_t flags;
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};
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/* Device run time data */
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struct i2c_sam_twihs_dev_data {
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struct k_sem sem;
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struct twihs_msg msg;
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};
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#define DEV_NAME(dev) ((dev)->config->name)
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#define DEV_CFG(dev) \
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((const struct i2c_sam_twihs_dev_cfg *const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct i2c_sam_twihs_dev_data *const)(dev)->driver_data)
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static int i2c_clk_set(Twihs *const twihs, u32_t speed)
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{
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u32_t ck_div = 0;
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u32_t cl_div;
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bool div_completed = false;
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/* From the datasheet "TWIHS Clock Waveform Generator Register"
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* T_low = ( ( CLDIV × 2^CKDIV ) + 3 ) × T_MCK
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*/
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while (!div_completed) {
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cl_div = ((SOC_ATMEL_SAM_MCK_FREQ_HZ / (2 * speed)) - 3)
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/ (1 << ck_div);
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if (cl_div <= 255) {
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div_completed = true;
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} else {
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ck_div++;
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}
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}
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if (ck_div > CKDIV_MAX) {
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SYS_LOG_ERR("Failed to configure I2C clock");
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return -EIO;
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}
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/* Set I2C bus clock duty cycle to 50% */
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twihs->TWIHS_CWGR = TWIHS_CWGR_CLDIV(cl_div) | TWIHS_CWGR_CHDIV(cl_div)
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| TWIHS_CWGR_CKDIV(ck_div);
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return 0;
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}
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static int i2c_sam_twihs_configure(struct device *dev, u32_t config)
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{
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const struct i2c_sam_twihs_dev_cfg *const dev_cfg = DEV_CFG(dev);
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Twihs *const twihs = dev_cfg->regs;
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u32_t bitrate;
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int ret;
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if (!(config & I2C_MODE_MASTER)) {
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SYS_LOG_ERR("Master Mode is not enabled");
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return -EIO;
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}
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if (config & I2C_ADDR_10_BITS) {
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SYS_LOG_ERR("I2C 10-bit addressing is currently not supported");
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SYS_LOG_ERR("Please submit a patch");
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return -EIO;
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}
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/* Configure clock */
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switch (I2C_SPEED_GET(config)) {
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case I2C_SPEED_STANDARD:
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bitrate = BUS_SPEED_STANDARD_HZ;
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break;
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case I2C_SPEED_FAST:
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bitrate = BUS_SPEED_FAST_HZ;
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break;
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default:
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SYS_LOG_ERR("Unsupported I2C speed value");
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return -EIO;
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}
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/* Setup clock waveform */
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ret = i2c_clk_set(twihs, bitrate);
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if (ret < 0) {
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return ret;
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}
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/* Disable Slave Mode */
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twihs->TWIHS_CR = TWIHS_CR_SVDIS;
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/* Enable Master Mode */
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twihs->TWIHS_CR = TWIHS_CR_MSEN;
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return 0;
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}
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static void write_msg_start(Twihs *const twihs, struct twihs_msg *msg,
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u8_t daddr)
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{
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/* Set slave address. */
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twihs->TWIHS_MMR = TWIHS_MMR_DADR(daddr);
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/* Write first data byte on I2C bus */
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twihs->TWIHS_THR = msg->buf[msg->idx++];
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/* Enable Transmit Ready and Transmission Completed interrupts */
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twihs->TWIHS_IER = TWIHS_IER_TXRDY | TWIHS_IER_TXCOMP | TWIHS_IER_NACK;
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}
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static void read_msg_start(Twihs *const twihs, struct twihs_msg *msg,
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u8_t daddr)
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{
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u32_t twihs_cr_stop;
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/* Set slave address and number of internal address bytes */
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twihs->TWIHS_MMR = TWIHS_MMR_MREAD | TWIHS_MMR_DADR(daddr);
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/* Enable Receive Ready and Transmission Completed interrupts */
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twihs->TWIHS_IER = TWIHS_IER_RXRDY | TWIHS_IER_TXCOMP | TWIHS_IER_NACK;
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/* In single data byte read the START and STOP must both be set */
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twihs_cr_stop = (msg->len == 1) ? TWIHS_CR_STOP : 0;
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/* Start the transfer by sending START condition */
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twihs->TWIHS_CR = TWIHS_CR_START | twihs_cr_stop;
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}
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static int i2c_sam_twihs_transfer(struct device *dev, struct i2c_msg *msgs,
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u8_t num_msgs, u16_t addr)
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{
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const struct i2c_sam_twihs_dev_cfg *const dev_cfg = DEV_CFG(dev);
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struct i2c_sam_twihs_dev_data *const dev_data = DEV_DATA(dev);
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Twihs *const twihs = dev_cfg->regs;
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__ASSERT_NO_MSG(msgs);
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if (!num_msgs) {
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return 0;
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}
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/* Clear pending interrupts, such as NACK. */
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(void)twihs->TWIHS_SR;
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/* Set number of internal address bytes to 0, not used. */
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twihs->TWIHS_IADR = 0;
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for (int i = 0; i < num_msgs; i++) {
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dev_data->msg.buf = msgs[i].buf;
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dev_data->msg.len = msgs[i].len;
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dev_data->msg.idx = 0;
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dev_data->msg.twihs_sr = 0;
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dev_data->msg.flags = msgs[i].flags;
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if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
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read_msg_start(twihs, &dev_data->msg, addr);
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} else {
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write_msg_start(twihs, &dev_data->msg, addr);
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}
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/* Wait for the transfer to complete */
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k_sem_take(&dev_data->sem, K_FOREVER);
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if (dev_data->msg.twihs_sr > 0) {
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/* Something went wrong */
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return -EIO;
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}
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}
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return 0;
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}
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static void i2c_sam_twihs_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct i2c_sam_twihs_dev_cfg *const dev_cfg = DEV_CFG(dev);
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struct i2c_sam_twihs_dev_data *const dev_data = DEV_DATA(dev);
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Twihs *const twihs = dev_cfg->regs;
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struct twihs_msg *msg = &dev_data->msg;
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u32_t isr_status;
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/* Retrieve interrupt status */
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isr_status = twihs->TWIHS_SR & twihs->TWIHS_IMR;
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/* Not Acknowledged */
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if (isr_status & TWIHS_SR_NACK) {
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msg->twihs_sr = isr_status;
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goto tx_comp;
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}
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/* Byte received */
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if (isr_status & TWIHS_SR_RXRDY) {
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msg->buf[msg->idx++] = twihs->TWIHS_RHR;
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if (msg->idx == msg->len - 1) {
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/* Send STOP condition */
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twihs->TWIHS_CR = TWIHS_CR_STOP;
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}
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}
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/* Byte sent */
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if (isr_status & TWIHS_SR_TXRDY) {
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if (msg->idx == msg->len) {
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if (msg->flags & I2C_MSG_STOP) {
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/* Send STOP condition */
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twihs->TWIHS_CR = TWIHS_CR_STOP;
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/* Disable Transmit Ready interrupt */
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twihs->TWIHS_IDR = TWIHS_IDR_TXRDY;
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} else {
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/* Transmission completed */
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goto tx_comp;
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}
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} else {
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twihs->TWIHS_THR = msg->buf[msg->idx++];
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}
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}
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/* Transmission completed */
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if (isr_status & TWIHS_SR_TXCOMP) {
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goto tx_comp;
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}
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return;
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tx_comp:
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/* Disable all enabled interrupts */
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twihs->TWIHS_IDR = twihs->TWIHS_IMR;
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/* We are done */
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k_sem_give(&dev_data->sem);
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}
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static int i2c_sam_twihs_initialize(struct device *dev)
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{
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const struct i2c_sam_twihs_dev_cfg *const dev_cfg = DEV_CFG(dev);
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struct i2c_sam_twihs_dev_data *const dev_data = DEV_DATA(dev);
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Twihs *const twihs = dev_cfg->regs;
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u32_t bitrate_cfg;
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int ret;
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/* Configure interrupts */
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dev_cfg->irq_config();
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/* Initialize semaphore */
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k_sem_init(&dev_data->sem, 0, 1);
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/* Connect pins to the peripheral */
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soc_gpio_list_configure(dev_cfg->pin_list, dev_cfg->pin_list_size);
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/* Enable module's clock */
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soc_pmc_peripheral_enable(dev_cfg->periph_id);
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/* Reset the module */
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twihs->TWIHS_CR = TWIHS_CR_SWRST;
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bitrate_cfg = _i2c_map_dt_bitrate(dev_cfg->bitrate);
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ret = i2c_sam_twihs_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
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if (ret < 0) {
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SYS_LOG_ERR("Failed to initialize %s device", DEV_NAME(dev));
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return ret;
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}
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/* Enable module's IRQ */
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irq_enable(dev_cfg->irq_id);
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SYS_LOG_INF("Device %s initialized", DEV_NAME(dev));
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return 0;
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}
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static const struct i2c_driver_api i2c_sam_twihs_driver_api = {
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.configure = i2c_sam_twihs_configure,
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.transfer = i2c_sam_twihs_transfer,
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};
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/* I2C0 */
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#ifdef CONFIG_I2C_0
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static struct device DEVICE_NAME_GET(i2c0_sam);
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static void i2c0_sam_irq_config(void)
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{
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IRQ_CONNECT(CONFIG_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI, i2c_sam_twihs_isr,
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DEVICE_GET(i2c0_sam), 0);
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}
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static const struct soc_gpio_pin pins_twihs0[] = PINS_TWIHS0;
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static const struct i2c_sam_twihs_dev_cfg i2c0_sam_config = {
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.regs = (Twihs *)CONFIG_I2C_0_BASE_ADDRESS,
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.irq_config = i2c0_sam_irq_config,
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.periph_id = CONFIG_I2C_0_PERIPHERAL_ID,
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.irq_id = CONFIG_I2C_0_IRQ,
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.pin_list = pins_twihs0,
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.pin_list_size = ARRAY_SIZE(pins_twihs0),
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.bitrate = CONFIG_I2C_0_BITRATE,
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};
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static struct i2c_sam_twihs_dev_data i2c0_sam_data;
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DEVICE_AND_API_INIT(i2c0_sam, CONFIG_I2C_0_NAME, &i2c_sam_twihs_initialize,
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&i2c0_sam_data, &i2c0_sam_config, POST_KERNEL,
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CONFIG_I2C_INIT_PRIORITY, &i2c_sam_twihs_driver_api);
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#endif
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/* I2C1 */
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#ifdef CONFIG_I2C_1
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static struct device DEVICE_NAME_GET(i2c1_sam);
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static void i2c1_sam_irq_config(void)
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{
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IRQ_CONNECT(CONFIG_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI, i2c_sam_twihs_isr,
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DEVICE_GET(i2c1_sam), 0);
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}
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static const struct soc_gpio_pin pins_twihs1[] = PINS_TWIHS1;
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static const struct i2c_sam_twihs_dev_cfg i2c1_sam_config = {
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.regs = (Twihs *)CONFIG_I2C_1_BASE_ADDRESS,
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.irq_config = i2c1_sam_irq_config,
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.periph_id = CONFIG_I2C_1_PERIPHERAL_ID,
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.irq_id = CONFIG_I2C_1_IRQ,
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.pin_list = pins_twihs1,
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.pin_list_size = ARRAY_SIZE(pins_twihs1),
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.bitrate = CONFIG_I2C_1_BITRATE,
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};
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static struct i2c_sam_twihs_dev_data i2c1_sam_data;
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DEVICE_AND_API_INIT(i2c1_sam, CONFIG_I2C_1_NAME, &i2c_sam_twihs_initialize,
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&i2c1_sam_data, &i2c1_sam_config, POST_KERNEL,
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CONFIG_I2C_INIT_PRIORITY, &i2c_sam_twihs_driver_api);
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#endif
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/* I2C2 */
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#ifdef CONFIG_I2C_2
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static struct device DEVICE_NAME_GET(i2c2_sam);
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static void i2c2_sam_irq_config(void)
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{
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IRQ_CONNECT(CONFIG_I2C_2_IRQ, CONFIG_I2C_2_IRQ_PRI, i2c_sam_twihs_isr,
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DEVICE_GET(i2c2_sam), 0);
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}
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static const struct soc_gpio_pin pins_twihs2[] = PINS_TWIHS2;
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static const struct i2c_sam_twihs_dev_cfg i2c2_sam_config = {
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.regs = (Twihs *)CONFIG_I2C_2_BASE_ADDRESS,
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.irq_config = i2c2_sam_irq_config,
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.periph_id = CONFIG_I2C_2_PERIPHERAL_ID,
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.irq_id = CONFIG_I2C_2_IRQ,
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.pin_list = pins_twihs2,
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.pin_list_size = ARRAY_SIZE(pins_twihs2),
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.bitrate = CONFIG_I2C_2_BITRATE,
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};
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static struct i2c_sam_twihs_dev_data i2c2_sam_data;
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DEVICE_AND_API_INIT(i2c2_sam, CONFIG_I2C_2_NAME, &i2c_sam_twihs_initialize,
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&i2c2_sam_data, &i2c2_sam_config, POST_KERNEL,
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CONFIG_I2C_INIT_PRIORITY, &i2c_sam_twihs_driver_api);
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#endif
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