52 lines
932 B
Plaintext
52 lines
932 B
Plaintext
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/xtensa.dtsi>
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#include <dt-bindings/i2c/i2c.h>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cadence,tensilica-xtensa-lx4";
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reg = <0>;
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};
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};
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sram0: memory@FF2C0000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xFF2C0000 DT_SIZE_K(96)>;
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};
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sram1: memory@FF300000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xFF300000 DT_SIZE_K(168)>;
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};
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soc {
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core_intc: core_intc@0 {
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compatible = "xtensa,core-intc";
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reg = <0x00 0x400>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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mailbox: mailbox@ff340018 {
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compatible = "intel,intel-adsp-mailbox";
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reg = <0xFF340018 0x30>;
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interrupts = <0x7 0 3>;
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interrupt-parent = <&core_intc>;
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label = "IPM_0";
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};
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};
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};
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