108 lines
2.8 KiB
YAML
108 lines
2.8 KiB
YAML
# Copyright (c) 2020 Hubert Miś <hubert.mis@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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description: FTDI FT800 graphic controller
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compatible: "ftdi,ft800"
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include: spi-device.yaml
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properties:
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irq-gpios:
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type: phandle-array
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required: false
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description: Optional IRQ line of FT800 controller
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pclk:
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type: int
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required: true
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description: |
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The value to divide the main clock by for PCLK. If the
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typical main clock was 48MHz and this value is 5, the PCLK
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will be 9.6 MHz. Must be positive value to enable the screen
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pclk_pol:
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type: int
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required: true
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description: |
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Polarity of PCLK. If it is set to zero, PCLK polarity is on
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the rising edge. If it is set to one, PCLK polarity is on
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the falling edge.
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cspread:
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type: int
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required: true
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description: |
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Controls the transition of RGB signals with PCLK active clock
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edge. When set to 0, R[7:2],G[7:2] and B[7:2] signals change
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following the active edge of PCLK. When set to 1, R[7:2]
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changes a PCLK clock early and B[7:2] a PCLK clock later,
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which helps reduce the system noise.
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swizzle:
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type: int
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required: true
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description: |
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Controls the arrangement of output RGB pins, which may help
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support different LCD panel. Please check FT800 Programmers
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Guide for details.
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vsize:
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type: int
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required: true
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description: Number of visible lines of pixels in one frame
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voffset:
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type: int
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required: true
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description: Number of invisible lines at the beginning of a new frame
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vcycle:
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type: int
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required: true
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description: |
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Number of all lines in a frame. It includes all visible and
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invisible lines at the beginning and at the end of a frame.
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vsync0:
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type: int
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required: true
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description: |
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Number of lines for the high state of signal VSYNC at
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the start of new frame.
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vsync1:
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type: int
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required: true
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description: |
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Number of lines for signal VSYNC toggle takes at the start
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of new frame.
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hsize:
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type: int
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required: true
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description: Number of PCLK cycles per visible part of horizontal line
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hoffset:
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type: int
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required: true
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description: |
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Number of PCLK cycles before pixels are scanned out for
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given line
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hcycle:
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type: int
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required: true
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description: Number of total PCLK cycles per horizontal line scan.
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hsync0:
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type: int
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required: true
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description: Number of PCLK cycles of HSYNC high state during start of
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line
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hsync1:
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type: int
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required: true
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description: Number of PCLK cycles for HSYNC toggle during start of line.
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