51 lines
1.1 KiB
Plaintext
51 lines
1.1 KiB
Plaintext
/*
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* Copyright (c) 2020 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/h7/stm32h7.dtsi>
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/ {
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soc {
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dmamux1: dmamux@40020800 {
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dma-requests= <107>;
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};
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};
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/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
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sram0: memory@24000000 {
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reg = <0x24000000 DT_SIZE_K(512)>;
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compatible = "mmio-sram";
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};
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/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
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sram1: memory@30000000 {
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reg = <0x30000000 DT_SIZE_K(128)>;
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compatible = "mmio-sram";
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};
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/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
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sram2: memory@30020000 {
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compatible = "mmio-sram";
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reg = <0x30020000 DT_SIZE_K(128)>;
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};
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/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
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sram3: memory@30040000 {
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compatible = "mmio-sram";
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reg = <0x30040000 DT_SIZE_K(32)>;
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};
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/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
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sram4: memory@38000000 {
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reg = <0x38000000 DT_SIZE_K(64)>;
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compatible = "mmio-sram";
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};
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dtcm: memory@20000000 {
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compatible = "arm,dtcm";
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reg = <0x20000000 DT_SIZE_K(128)>;
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};
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};
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