78 lines
1.7 KiB
Plaintext
78 lines
1.7 KiB
Plaintext
/*
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* Copyright (c) 2021 SILA Embedded Solutions GmbH
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/h7/stm32h7.dtsi>
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/ {
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soc {
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flash-controller@52002000 {
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flash0: flash@8000000 {
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write-block-size = <32>;
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erase-block-size = <DT_SIZE_K(128)>;
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};
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};
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uart9: serial@40011800 {
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compatible = "st,stm32-uart";
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reg = <0x40011800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
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interrupts = <155 0>;
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status = "disabled";
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label = "UART_9";
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};
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usart10: serial@40011c00 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40011c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
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interrupts = <156 0>;
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status = "disabled";
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label = "UART_10";
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};
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dmamux1: dmamux@40020800 {
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dma-requests= <129>;
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};
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cryp: cryp@48021000 {
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compatible = "st,stm32-cryp";
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reg = <0x48021000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
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interrupts = <79 0>;
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status = "disabled";
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label = "CRYP";
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};
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};
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/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
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sram0: memory@24000000 {
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reg = <0x24000000 DT_SIZE_K(320)>;
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compatible = "mmio-sram";
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};
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/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
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sram1: memory@30000000 {
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reg = <0x30000000 DT_SIZE_K(16)>;
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compatible = "mmio-sram";
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};
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/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
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sram2: memory@30040000 {
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reg = <0x30040000 DT_SIZE_K(16)>;
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compatible = "mmio-sram";
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};
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/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
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sram4: memory@38000000 {
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reg = <0x38000000 DT_SIZE_K(16)>;
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compatible = "mmio-sram";
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};
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dtcm: memory@20000000 {
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compatible = "arm,dtcm";
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reg = <0x20000000 DT_SIZE_K(128)>;
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};
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};
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