37 lines
860 B
C
37 lines
860 B
C
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <kernel.h>
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static int soc_init(struct device *dev)
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{
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__IO uint32_t *girc_enable_set;
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__enable_irq();
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/* Enable clocks for Interrupts and CPU */
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PCR_INST->CLK_REQ_1_b.INT_CLK_REQ = 1;
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PCR_INST->CLK_REQ_1_b.PROCESSOR_CLK_REQ = 1;
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/* Route all interrupts from EC to NVIC */
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EC_REG_BANK_INST->INTERRUPT_CONTROL = 0x1;
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for (girc_enable_set = (uint32_t *)&INTS_INST->GIRQ08_EN_SET;
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girc_enable_set <= &INTS_INST->GIRQ15_EN_SET;
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girc_enable_set += 5) {
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/* This probably will require tunning, but drawing 8.2 also
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illustrates how to diasable spurious interrupts */
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*girc_enable_set = 0xFFFFFFFF;
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}
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return 0;
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}
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SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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