226 lines
4.4 KiB
Plaintext
226 lines
4.4 KiB
Plaintext
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/intel/intel_cavs.dtsi>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx4";
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reg = <0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx4";
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reg = <1>;
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};
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};
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sram0: memory@be000000 {
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compatible = "mmio-sram";
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reg = <0xbe000000 DT_SIZE_K(512)>;
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};
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sram1: memory@be800000 {
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compatible = "mmio-sram";
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reg = <0xbe800000 DT_SIZE_K(128)>;
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};
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sysclk: system-clock {
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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#clock-cells = <0>;
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};
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audioclk: audio-clock {
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compatible = "fixed-clock";
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clock-frequency = <24576000>;
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#clock-cells = <0>;
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};
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pllclk: pll-clock {
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compatible = "fixed-clock";
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clock-frequency = <96000000>;
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#clock-cells = <0>;
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};
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soc {
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shim: shim@1000 {
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compatible = "intel,cavs-shim";
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reg = <0x1000 0x100>;
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};
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win: win@1580 {
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compatible = "intel,cavs-win";
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reg = <0x1580 0x20>;
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};
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core_intc: core_intc@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0x00 0x400>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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cavs_host_ipc: cavs_host_ipc@1180 {
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compatible = "intel,cavs-host-ipc";
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reg = <0x1180 0x30>;
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interrupts = <7 0 0>;
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interrupt-parent = <&cavs0>;
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};
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cavs0: cavs@1600 {
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compatible = "intel,cavs-intc";
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reg = <0x1600 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <6 0 0>;
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interrupt-parent = <&core_intc>;
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label = "CAVS_0";
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};
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cavs1: cavs@1610 {
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compatible = "intel,cavs-intc";
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reg = <0x1610 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0xA 0 0>;
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interrupt-parent = <&core_intc>;
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label = "CAVS_1";
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};
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cavs2: cavs@1620 {
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compatible = "intel,cavs-intc";
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reg = <0x1620 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0XD 0 0>;
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interrupt-parent = <&core_intc>;
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label = "CAVS_2";
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};
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cavs3: cavs@1630 {
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compatible = "intel,cavs-intc";
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reg = <0x1630 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0x10 0 0>;
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interrupt-parent = <&core_intc>;
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label = "CAVS_3";
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};
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idc: idc@1200 {
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compatible = "intel,cavs-idc";
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label = "CAVS_IDC";
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reg = <0x1200 0x80>;
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interrupts = <8 0 0>;
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interrupt-parent = <&cavs0>;
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};
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ssp0: ssp@8000 {
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compatible = "intel,ssp-dai";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00008000 0x200
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0x00008E00 0x008>;
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interrupts = <0x01 0 0>;
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interrupt-parent = <&cavs3>;
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dmas = <&lpgpdma0 2
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&lpgpdma0 3>;
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dma-names = "tx", "rx";
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label = "SSP_0";
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status = "okay";
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};
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ssp1: ssp@8200 {
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compatible = "intel,ssp-dai";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00008200 0x200
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0x00008E00 0x008>;
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interrupts = <0x01 0 0>;
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interrupt-parent = <&cavs3>;
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dmas = <&lpgpdma0 4
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&lpgpdma0 5>;
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dma-names = "tx", "rx";
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label = "SSP_1";
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status = "okay";
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};
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ssp2: ssp@8400 {
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compatible = "intel,ssp-dai";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00008400 0x200
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0x00008E00 0x008>;
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interrupts = <0x02 0 0>;
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interrupt-parent = <&cavs3>;
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dmas = <&lpgpdma0 6
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&lpgpdma0 7>;
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dma-names = "tx", "rx";
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label = "SSP_2";
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status = "okay";
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};
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ssp3: ssp@8600 {
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compatible = "intel,ssp-dai";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00008600 0x200
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0x00008E00 0x008>;
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interrupts = <0x03 0 0>;
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interrupt-parent = <&cavs3>;
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dmas = <&lpgpdma0 8
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&lpgpdma0 9>;
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dma-names = "tx", "rx";
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label = "SSP_3";
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status = "okay";
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};
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ssp4: ssp@8800 {
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compatible = "intel,ssp-dai";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00008800 0x200
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0x00008E00 0x008>;
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interrupts = <0x03 0 0>;
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interrupt-parent = <&cavs3>;
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dmas = <&lpgpdma0 10
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&lpgpdma0 11>;
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dma-names = "tx", "rx";
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label = "SSP_4";
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status = "okay";
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};
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ssp5: ssp@8a00 {
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compatible = "intel,ssp-dai";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00008A00 0x200
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0x00008E00 0x008>;
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interrupts = <0x03 0 0>;
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interrupt-parent = <&cavs3>;
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dmas = <&lpgpdma0 12
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&lpgpdma0 13>;
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dma-names = "tx", "rx";
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label = "SSP_5";
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status = "okay";
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};
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};
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};
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