212 lines
6.7 KiB
C
212 lines
6.7 KiB
C
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Wrapper of NXP Mailbox driver for Zephyr's MBOX model.
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/mbox.h>
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#include <zephyr/irq.h>
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#include <zephyr/sys/util_macro.h>
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#include <fsl_mailbox.h>
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#define LOG_LEVEL CONFIG_MBOX_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(nxp_mbox_mailbox);
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#define DT_DRV_COMPAT nxp_mbox_mailbox
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#define MAILBOX_MAX_CHANNELS 4
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#define MAILBOX_MBOX_SIZE 3
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#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
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#ifdef LPC55S69_cm33_core0_SERIES
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#define MAILBOX_ID_THIS_CPU kMAILBOX_CM33_Core0
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#define MAILBOX_ID_OTHER_CPU kMAILBOX_CM33_Core1
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#else
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#define MAILBOX_ID_THIS_CPU kMAILBOX_CM33_Core1
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#define MAILBOX_ID_OTHER_CPU kMAILBOX_CM33_Core0
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#endif
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#else
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#if defined(__CM4_CMSIS_VERSION)
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#define MAILBOX_ID_THIS_CPU kMAILBOX_CM4
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#define MAILBOX_ID_OTHER_CPU kMAILBOX_CM0Plus
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#else
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#define MAILBOX_ID_THIS_CPU kMAILBOX_CM0Plus
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#define MAILBOX_ID_OTHER_CPU kMAILBOX_CM4
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#endif
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#endif
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#define GENIRQ_SHIFT (28U)
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#define GEN0_IRQ_TRIGGER BIT(GENIRQ_SHIFT + 3U) /*!< General interrupt 3. */
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#define GEN1_IRQ_TRIGGER BIT(GENIRQ_SHIFT + 2U) /*!< General interrupt 2. */
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#define GEN2_IRQ_TRIGGER BIT(GENIRQ_SHIFT + 1U) /*!< General interrupt 1. */
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#define GEN3_IRQ_TRIGGER BIT(GENIRQ_SHIFT + 0U) /*!< General interrupt 0. */
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#define DATA_MASK BIT_MASK(24U)
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#define DATAIRQ_SHIFT (24U)
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#define DATA0_IRQ_TRIGGER BIT(DATAIRQ_SHIFT + 3U) /*!< Data interrupt 3. */
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#define DATA1_IRQ_TRIGGER BIT(DATAIRQ_SHIFT + 2U) /*!< Data interrupt 2. */
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#define DATA2_IRQ_TRIGGER BIT(DATAIRQ_SHIFT + 1U) /*!< Data interrupt 1. */
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#define DATA3_IRQ_TRIGGER BIT(DATAIRQ_SHIFT + 0U) /*!< Data interrupt 0. */
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struct nxp_mailbox_data {
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mbox_callback_t cb[MAILBOX_MAX_CHANNELS];
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void *user_data[MAILBOX_MAX_CHANNELS];
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bool channel_enable[MAILBOX_MAX_CHANNELS];
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uint32_t received_data;
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};
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struct nxp_mailbox_config {
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MAILBOX_Type *base;
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};
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static void mailbox_isr(const struct device *dev)
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{
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struct nxp_mailbox_data *data = dev->data;
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const struct nxp_mailbox_config *config = dev->config;
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mailbox_cpu_id_t cpu_id;
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cpu_id = MAILBOX_ID_THIS_CPU;
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volatile uint32_t mailbox_value = MAILBOX_GetValue(config->base, cpu_id);
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uint32_t flags = mailbox_value & (~DATA_MASK);
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/* Clear or the interrupt gets called intermittently */
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MAILBOX_ClearValueBits(config->base, cpu_id, mailbox_value);
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for (int i_channel = 0; i_channel < MAILBOX_MAX_CHANNELS; i_channel++) {
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/* Continue to next channel if channel is not enabled */
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if (!data->channel_enable[i_channel]) {
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continue;
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}
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if ((flags & (DATA0_IRQ_TRIGGER >> i_channel))) {
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data->received_data = mailbox_value & DATA_MASK;
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struct mbox_msg msg = {(const void *)&data->received_data,
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MAILBOX_MBOX_SIZE};
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if (data->cb[i_channel]) {
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data->cb[i_channel](dev, i_channel, data->user_data[i_channel],
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&msg);
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}
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} else if ((flags & (GEN0_IRQ_TRIGGER >> i_channel))) {
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if (data->cb[i_channel]) {
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data->cb[i_channel](dev, i_channel, data->user_data[i_channel],
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NULL);
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}
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}
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}
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F
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* Store immediate overlapping exception return operation
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* might vector to incorrect interrupt
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*/
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#if defined __CORTEX_M && (__CORTEX_M == 4U)
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barrier_dsync_fence_full();
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#endif
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}
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static int nxp_mailbox_send(const struct device *dev, uint32_t channel, const struct mbox_msg *msg)
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{
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uint32_t __aligned(4) data32;
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const struct nxp_mailbox_config *cfg = dev->config;
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if (channel >= MAILBOX_MAX_CHANNELS) {
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return -EINVAL;
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}
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/* Signalling mode. */
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if (msg == NULL) {
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MAILBOX_SetValueBits(cfg->base, MAILBOX_ID_OTHER_CPU, GEN0_IRQ_TRIGGER >> channel);
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return 0;
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}
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/* Data transfer mode. */
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if (msg->size != MAILBOX_MBOX_SIZE) {
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/* We can only send this many bytes at a time. */
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return -EMSGSIZE;
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}
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/* memcpy to avoid issues when msg->data is not word-aligned. */
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memcpy(&data32, msg->data, msg->size);
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MAILBOX_SetValueBits(cfg->base, MAILBOX_ID_OTHER_CPU,
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(DATA0_IRQ_TRIGGER >> channel) | (data32 & DATA_MASK));
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return 0;
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}
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static int nxp_mailbox_register_callback(const struct device *dev, uint32_t channel,
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mbox_callback_t cb, void *user_data)
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{
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struct nxp_mailbox_data *data = dev->data;
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if (channel >= MAILBOX_MAX_CHANNELS) {
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return -EINVAL;
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}
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data->cb[channel] = cb;
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data->user_data[channel] = user_data;
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return 0;
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}
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static int nxp_mailbox_mtu_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return MAILBOX_MBOX_SIZE;
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}
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static uint32_t nxp_mailbox_max_channels_get(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return MAILBOX_MAX_CHANNELS;
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}
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static int nxp_mailbox_set_enabled(const struct device *dev, uint32_t channel, bool enable)
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{
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struct nxp_mailbox_data *data = dev->data;
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if (channel >= MAILBOX_MAX_CHANNELS) {
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return -EINVAL;
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}
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data->channel_enable[channel] = enable;
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return 0;
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}
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static const struct mbox_driver_api nxp_mailbox_driver_api = {
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.send = nxp_mailbox_send,
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.register_callback = nxp_mailbox_register_callback,
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.mtu_get = nxp_mailbox_mtu_get,
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.max_channels_get = nxp_mailbox_max_channels_get,
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.set_enabled = nxp_mailbox_set_enabled,
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};
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#define MAILBOX_INSTANCE_DEFINE(idx) \
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static struct nxp_mailbox_data nxp_mailbox_##idx##_data; \
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const static struct nxp_mailbox_config nxp_mailbox_##idx##_config = { \
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.base = (MAILBOX_Type *)DT_INST_REG_ADDR(idx), \
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}; \
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static int nxp_mailbox_##idx##_init(const struct device *dev) \
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{ \
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ARG_UNUSED(dev); \
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MAILBOX_Init(nxp_mailbox_##idx##_config.base); \
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IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), mailbox_isr, \
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DEVICE_DT_INST_GET(idx), 0); \
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irq_enable(DT_INST_IRQN(idx)); \
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return 0; \
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} \
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DEVICE_DT_INST_DEFINE(idx, nxp_mailbox_##idx##_init, NULL, &nxp_mailbox_##idx##_data, \
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&nxp_mailbox_##idx##_config, POST_KERNEL, CONFIG_MBOX_INIT_PRIORITY, \
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&nxp_mailbox_driver_api)
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#define MAILBOX_INST(idx) MAILBOX_INSTANCE_DEFINE(idx);
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DT_INST_FOREACH_STATUS_OKAY(MAILBOX_INST)
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