349 lines
8.5 KiB
C
349 lines
8.5 KiB
C
/*
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* Copyright (c) 2018 Justin Watson
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* Copyright (c) 2023 Gerson Fernando Budke
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam_gpio
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
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#include <zephyr/dt-bindings/gpio/atmel-sam-gpio.h>
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#include <zephyr/irq.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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typedef void (*config_func_t)(const struct device *dev);
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struct gpio_sam_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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Pio *regs;
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config_func_t config_func;
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const struct atmel_sam_pmc_config clock_cfg;
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};
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struct gpio_sam_runtime {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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sys_slist_t cb;
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};
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#define GPIO_SAM_ALL_PINS 0xFFFFFFFF
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static int gpio_sam_port_configure(const struct device *dev, uint32_t mask,
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gpio_flags_t flags)
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{
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const struct gpio_sam_config * const cfg = dev->config;
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Pio * const pio = cfg->regs;
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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if ((flags & GPIO_LINE_OPEN_DRAIN) != 0) {
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/* Enable open-drain drive mode */
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pio->PIO_MDER = mask;
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} else {
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/* Open-drain is the only supported single-ended mode */
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return -ENOTSUP;
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}
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} else {
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/* Disable open-drain drive mode */
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pio->PIO_MDDR = mask;
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}
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if (!(flags & (GPIO_OUTPUT | GPIO_INPUT))) {
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/* Neither input nor output mode is selected */
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/* Disable the interrupt. */
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pio->PIO_IDR = mask;
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/* Disable pull-up. */
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pio->PIO_PUDR = mask;
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#if defined(CONFIG_SOC_SERIES_SAM4S) || \
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defined(CONFIG_SOC_SERIES_SAM4E) || \
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defined(CONFIG_SOC_SERIES_SAME70) || \
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defined(CONFIG_SOC_SERIES_SAMV71)
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/* Disable pull-down. */
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pio->PIO_PPDDR = mask;
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#endif
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/* Let the PIO control the pin (instead of a peripheral). */
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pio->PIO_PER = mask;
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/* Disable output. */
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pio->PIO_ODR = mask;
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return 0;
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}
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/* Setup the pin direction. */
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if (flags & GPIO_OUTPUT) {
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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/* Set the pin. */
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pio->PIO_SODR = mask;
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}
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if (flags & GPIO_OUTPUT_INIT_LOW) {
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/* Clear the pin. */
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pio->PIO_CODR = mask;
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}
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/* Enable the output */
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pio->PIO_OER = mask;
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/* Enable direct control of output level via PIO_ODSR */
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pio->PIO_OWER = mask;
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} else {
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/* Disable the output */
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pio->PIO_ODR = mask;
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}
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/* Note: Input is always enabled. */
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/* Setup selected Pull resistor.
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*
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* A pull cannot be enabled if the opposite pull is enabled.
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* Clear both pulls, then enable the one we need.
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*/
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pio->PIO_PUDR = mask;
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#if defined(CONFIG_SOC_SERIES_SAM4S) || \
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defined(CONFIG_SOC_SERIES_SAM4E) || \
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defined(CONFIG_SOC_SERIES_SAME70) || \
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defined(CONFIG_SOC_SERIES_SAMV71)
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pio->PIO_PPDDR = mask;
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#endif
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if (flags & GPIO_PULL_UP) {
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/* Enable pull-up. */
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pio->PIO_PUER = mask;
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#if defined(CONFIG_SOC_SERIES_SAM4S) || \
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defined(CONFIG_SOC_SERIES_SAM4E) || \
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defined(CONFIG_SOC_SERIES_SAME70) || \
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defined(CONFIG_SOC_SERIES_SAMV71)
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/* Setup Pull-down resistor. */
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} else if (flags & GPIO_PULL_DOWN) {
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/* Enable pull-down. */
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pio->PIO_PPDER = mask;
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#endif
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}
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#if defined(CONFIG_SOC_SERIES_SAM3X)
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/* Setup debounce. */
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if (flags & SAM_GPIO_DEBOUNCE) {
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pio->PIO_DIFSR = mask;
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} else {
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pio->PIO_SCIFSR = mask;
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}
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#elif defined(CONFIG_SOC_SERIES_SAM4S) || \
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defined(CONFIG_SOC_SERIES_SAM4E) || \
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defined(CONFIG_SOC_SERIES_SAME70) || \
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defined(CONFIG_SOC_SERIES_SAMV71)
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/* Setup debounce. */
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if (flags & SAM_GPIO_DEBOUNCE) {
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pio->PIO_IFSCER = mask;
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} else {
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pio->PIO_IFSCDR = mask;
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}
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#endif
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/* Enable the PIO to control the pin (instead of a peripheral). */
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pio->PIO_PER = mask;
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return 0;
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}
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static int gpio_sam_config(const struct device *dev, gpio_pin_t pin,
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gpio_flags_t flags)
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{
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return gpio_sam_port_configure(dev, BIT(pin), flags);
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}
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static int gpio_sam_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_sam_config * const cfg = dev->config;
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Pio * const pio = cfg->regs;
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*value = pio->PIO_PDSR;
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return 0;
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}
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static int gpio_sam_port_set_masked_raw(const struct device *dev,
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uint32_t mask,
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uint32_t value)
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{
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const struct gpio_sam_config * const cfg = dev->config;
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Pio * const pio = cfg->regs;
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pio->PIO_ODSR = (pio->PIO_ODSR & ~mask) | (mask & value);
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return 0;
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}
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static int gpio_sam_port_set_bits_raw(const struct device *dev, uint32_t mask)
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{
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const struct gpio_sam_config * const cfg = dev->config;
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Pio * const pio = cfg->regs;
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/* Set pins. */
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pio->PIO_SODR = mask;
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return 0;
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}
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static int gpio_sam_port_clear_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_sam_config * const cfg = dev->config;
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Pio * const pio = cfg->regs;
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/* Clear pins. */
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pio->PIO_CODR = mask;
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return 0;
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}
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static int gpio_sam_port_toggle_bits(const struct device *dev, uint32_t mask)
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{
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const struct gpio_sam_config * const cfg = dev->config;
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Pio * const pio = cfg->regs;
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/* Toggle pins. */
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pio->PIO_ODSR ^= mask;
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return 0;
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}
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static int gpio_sam_port_interrupt_configure(const struct device *dev,
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uint32_t mask,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_sam_config * const cfg = dev->config;
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Pio * const pio = cfg->regs;
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/* Disable the interrupt. */
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pio->PIO_IDR = mask;
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/* Disable additional interrupt modes. */
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pio->PIO_AIMDR = mask;
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if (trig != GPIO_INT_TRIG_BOTH) {
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/* Enable additional interrupt modes to support single
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* edge/level detection.
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*/
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pio->PIO_AIMER = mask;
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if (mode == GPIO_INT_MODE_EDGE) {
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pio->PIO_ESR = mask;
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} else {
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pio->PIO_LSR = mask;
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}
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uint32_t rising_edge;
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if (trig == GPIO_INT_TRIG_HIGH) {
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rising_edge = mask;
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} else {
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rising_edge = ~mask;
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}
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/* Set to high-level or rising edge. */
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pio->PIO_REHLSR = rising_edge & mask;
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/* Set to low-level or falling edge. */
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pio->PIO_FELLSR = ~rising_edge & mask;
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}
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if (mode != GPIO_INT_MODE_DISABLED) {
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/* Clear any pending interrupts */
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(void)pio->PIO_ISR;
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/* Enable the interrupt. */
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pio->PIO_IER = mask;
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}
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return 0;
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}
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static int gpio_sam_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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return gpio_sam_port_interrupt_configure(dev, BIT(pin), mode, trig);
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}
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static void gpio_sam_isr(const struct device *dev)
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{
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const struct gpio_sam_config * const cfg = dev->config;
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Pio * const pio = cfg->regs;
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struct gpio_sam_runtime *context = dev->data;
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uint32_t int_stat;
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int_stat = pio->PIO_ISR;
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gpio_fire_callbacks(&context->cb, dev, int_stat);
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}
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static int gpio_sam_manage_callback(const struct device *port,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_sam_runtime *context = port->data;
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return gpio_manage_callback(&context->cb, callback, set);
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}
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static const struct gpio_driver_api gpio_sam_api = {
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.pin_configure = gpio_sam_config,
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.port_get_raw = gpio_sam_port_get_raw,
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.port_set_masked_raw = gpio_sam_port_set_masked_raw,
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.port_set_bits_raw = gpio_sam_port_set_bits_raw,
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.port_clear_bits_raw = gpio_sam_port_clear_bits_raw,
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.port_toggle_bits = gpio_sam_port_toggle_bits,
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.pin_interrupt_configure = gpio_sam_pin_interrupt_configure,
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.manage_callback = gpio_sam_manage_callback,
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};
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int gpio_sam_init(const struct device *dev)
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{
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const struct gpio_sam_config * const cfg = dev->config;
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/* Enable GPIO clock in PMC. This is necessary to enable interrupts */
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(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
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(clock_control_subsys_t)&cfg->clock_cfg);
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cfg->config_func(dev);
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return 0;
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}
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#define GPIO_SAM_INIT(n) \
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static void port_##n##_sam_config_func(const struct device *dev); \
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\
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static const struct gpio_sam_config port_##n##_sam_config = { \
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
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}, \
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.regs = (Pio *)DT_INST_REG_ADDR(n), \
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.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n), \
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.config_func = port_##n##_sam_config_func, \
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}; \
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\
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static struct gpio_sam_runtime port_##n##_sam_runtime; \
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\
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DEVICE_DT_INST_DEFINE(n, gpio_sam_init, NULL, \
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&port_##n##_sam_runtime, \
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&port_##n##_sam_config, PRE_KERNEL_1, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_sam_api); \
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\
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static void port_##n##_sam_config_func(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
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gpio_sam_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(GPIO_SAM_INIT)
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