263 lines
6.2 KiB
C
263 lines
6.2 KiB
C
/*
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* Copyright (c) 2022 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_mpfs_gpio
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/irq.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#define MSS_GPIO_INPUT_MODE 0x02
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#define MSS_GPIO_OUTPUT_MODE 0x05
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#define MSS_GPIO_INOUT_MODE 0x03
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#define MSS_GPIO_IRQ_LEVEL_HIGH 0x00
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#define MSS_GPIO_IRQ_LEVEL_LOW 0x20
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#define MSS_GPIO_IRQ_EDGE_POSITIVE 0x40
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#define MSS_GPIO_IRQ_EDGE_NEGATIVE 0x60
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#define MSS_GPIO_IRQ_EDGE_BOTH 0x80
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#define MSS_GPIO_INT_ENABLE_MASK 0x08
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#define MSS_OUTPUT_BUFFER_ENABLE_MASK 0x04
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struct mss_gpio_t {
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uint32_t gpio_cfg[32];
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uint32_t gpio_irq;
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const uint32_t gpio_in;
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uint32_t gpio_out;
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uint32_t gpio_cfg_all;
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uint32_t gpio_cfg_byte[4];
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uint32_t gpio_clr_bits;
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uint32_t gpio_set_bits;
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};
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typedef void (*mss_gpio_cfg_func_t)(void);
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struct mss_gpio_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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uintptr_t gpio_base_addr;
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uint32_t gpio_irq_base;
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mss_gpio_cfg_func_t gpio_cfg_func;
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};
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struct mss_gpio_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* list of callbacks */
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sys_slist_t cb;
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};
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/* Helper Macros for GPIO */
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#define DEV_GPIO_CFG(dev) \
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((const struct mss_gpio_config * const)(dev)->config)
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#define DEV_GPIO(dev) \
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((volatile struct mss_gpio_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
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#define DEV_GPIO_DATA(dev) \
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((struct mss_gpio_data *)(dev)->data)
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static int mss_gpio_config(const struct device *dev,
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gpio_pin_t pin,
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gpio_flags_t flags)
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{
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volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
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uint32_t io_flags = flags & (GPIO_INPUT | GPIO_OUTPUT);
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if (io_flags == GPIO_DISCONNECTED) {
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return -ENOTSUP;
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}
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if (flags & GPIO_OUTPUT) {
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gpio->gpio_cfg[pin] |= MSS_GPIO_OUTPUT_MODE;
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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gpio->gpio_out |= BIT(pin);
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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gpio->gpio_out &= ~BIT(pin);
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}
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} else if (flags & GPIO_INPUT) {
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gpio->gpio_cfg[pin] |= MSS_GPIO_INPUT_MODE;
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} else {
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return -ENOTSUP;
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}
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return 0;
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}
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static int mss_gpio_port_toggle_bits(const struct device *dev,
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gpio_port_pins_t mask)
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{
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volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
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gpio->gpio_out ^= mask;
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return 0;
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}
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static int mss_gpio_port_get_raw(const struct device *dev,
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gpio_port_value_t *value)
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{
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volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
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*value = gpio->gpio_in;
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return 0;
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}
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static int mss_gpio_port_set_masked_raw(const struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
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gpio->gpio_out = (gpio->gpio_out & ~mask) | (value & mask);
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return 0;
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}
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static int mss_gpio_port_set_bits_raw(const struct device *dev,
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gpio_port_pins_t mask)
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{
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volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
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gpio->gpio_out |= mask;
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return 0;
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}
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static int mss_gpio_port_clear_bits_raw(const struct device *dev,
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gpio_port_pins_t mask)
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{
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volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
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gpio->gpio_out &= ~mask;
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return 0;
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}
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static int mss_gpio_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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ARG_UNUSED(trig);
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volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
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gpio->gpio_cfg[pin] |= (MSS_GPIO_INT_ENABLE_MASK);
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switch (mode | trig) {
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case GPIO_INT_EDGE_BOTH:
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gpio->gpio_cfg[pin] |= (MSS_GPIO_IRQ_EDGE_BOTH);
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break;
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case GPIO_INT_EDGE_RISING:
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gpio->gpio_cfg[pin] |= (MSS_GPIO_IRQ_EDGE_POSITIVE);
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break;
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case GPIO_INT_EDGE_FALLING:
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gpio->gpio_cfg[pin] |= (MSS_GPIO_IRQ_EDGE_NEGATIVE);
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break;
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case GPIO_INT_LEVEL_LOW:
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gpio->gpio_cfg[pin] |= (MSS_GPIO_IRQ_LEVEL_LOW);
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break;
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case GPIO_INT_LEVEL_HIGH:
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gpio->gpio_cfg[pin] |= (MSS_GPIO_IRQ_LEVEL_HIGH);
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break;
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default:
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gpio->gpio_cfg[pin] &= ~MSS_GPIO_INT_ENABLE_MASK;
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break;
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}
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return 0;
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}
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static int mss_gpio_manage_callback(const struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct mss_gpio_data *data = dev->data;
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return gpio_manage_callback(&data->cb, callback, set);
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}
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static const struct gpio_driver_api mss_gpio_driver = {
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.pin_configure = mss_gpio_config,
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.port_toggle_bits = mss_gpio_port_toggle_bits,
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.port_get_raw = mss_gpio_port_get_raw,
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.port_set_masked_raw = mss_gpio_port_set_masked_raw,
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.port_set_bits_raw = mss_gpio_port_set_bits_raw,
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.port_clear_bits_raw = mss_gpio_port_clear_bits_raw,
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.pin_interrupt_configure = mss_gpio_pin_interrupt_configure,
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.manage_callback = mss_gpio_manage_callback
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};
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static int mss_gpio_init(const struct device *dev)
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{
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volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
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gpio->gpio_irq = 0xFFFFFFFFU;
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const struct mss_gpio_config *cfg = DEV_GPIO_CFG(dev);
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/* Configure GPIO device */
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cfg->gpio_cfg_func();
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return 0;
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}
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static void mss_gpio_irq_handler(const struct device *dev)
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{
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volatile struct mss_gpio_t *gpio = DEV_GPIO(dev);
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uint32_t interrupt_status = gpio->gpio_irq;
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gpio->gpio_irq = gpio->gpio_irq;
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struct mss_gpio_data *data = dev->data;
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gpio_fire_callbacks(&data->cb, dev, interrupt_status);
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}
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#define MSS_GPIO_INIT(n) \
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static struct mss_gpio_data mss_gpio_data_##n; \
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static void gpio_mss_gpio_cfg_func_##n(void); \
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\
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static const struct mss_gpio_config mss_gpio_config_##n = { \
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.gpio_base_addr = DT_INST_REG_ADDR(n), \
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.gpio_irq_base = DT_INST_IRQN(n), \
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.gpio_cfg_func = gpio_mss_gpio_cfg_func_##n \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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mss_gpio_init, \
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NULL, \
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&mss_gpio_data_##n, &mss_gpio_config_##n, \
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PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
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&mss_gpio_driver); \
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\
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static void gpio_mss_gpio_cfg_func_##n(void) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), \
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DT_INST_IRQ(n, priority), \
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mss_gpio_irq_handler, \
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DEVICE_DT_INST_GET(n), \
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0); \
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irq_enable(DT_INST_IRQN(n)); \
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} \
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DT_INST_FOREACH_STATUS_OKAY(MSS_GPIO_INIT)
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