331 lines
7.4 KiB
C
331 lines
7.4 KiB
C
/*
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* Copyright (c) 2022 ASPEED Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/syscon.h>
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#include <zephyr/sys/barrier.h>
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/*
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* cache area control: each bit controls 32KB cache area
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* 1: cacheable
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* 0: no-cache
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*
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* bit[0]: 1st 32KB from 0x0000_0000 to 0x0000_7fff
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* bit[1]: 2nd 32KB from 0x0000_8000 to 0x0000_ffff
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* ...
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* bit[22]: 23th 32KB from 0x000a_8000 to 0x000a_ffff
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* bit[23]: 24th 32KB from 0x000b_0000 to 0x000b_ffff
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*/
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#define CACHE_AREA_CTRL_REG 0xa50
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#define CACHE_INVALID_REG 0xa54
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#define CACHE_FUNC_CTRL_REG 0xa58
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#define CACHED_SRAM_ADDR CONFIG_SRAM_BASE_ADDRESS
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#define CACHED_SRAM_SIZE KB(CONFIG_SRAM_SIZE)
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#define CACHED_SRAM_END (CACHED_SRAM_ADDR + CACHED_SRAM_SIZE - 1)
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#define CACHE_AREA_SIZE_LOG2 15
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#define CACHE_AREA_SIZE (1 << CACHE_AREA_SIZE_LOG2)
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#define DCACHE_INVALID(addr) (BIT(31) | ((addr & GENMASK(10, 0)) << 16))
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#define ICACHE_INVALID(addr) (BIT(15) | ((addr & GENMASK(10, 0)) << 0))
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#define ICACHE_CLEAN BIT(2)
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#define DCACHE_CLEAN BIT(1)
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#define CACHE_ENABLE BIT(0)
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/* cache size = 32B * 128 = 4KB */
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#define CACHE_LINE_SIZE_LOG2 5
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#define CACHE_LINE_SIZE (1 << CACHE_LINE_SIZE_LOG2)
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#define N_CACHE_LINE 128
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#define CACHE_ALIGNED_ADDR(addr) \
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((addr >> CACHE_LINE_SIZE_LOG2) << CACHE_LINE_SIZE_LOG2)
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/* prefetch buffer */
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#define PREFETCH_BUF_SIZE CACHE_LINE_SIZE
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static void aspeed_cache_init(void)
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{
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const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
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uint32_t start_bit, end_bit, max_bit;
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/* set all cache areas to no-cache by default */
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syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, 0);
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/* calculate how many areas need to be set */
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max_bit = 8 * sizeof(uint32_t) - 1;
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start_bit = MIN(max_bit, CACHED_SRAM_ADDR >> CACHE_AREA_SIZE_LOG2);
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end_bit = MIN(max_bit, CACHED_SRAM_END >> CACHE_AREA_SIZE_LOG2);
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syscon_write_reg(dev, CACHE_AREA_CTRL_REG, GENMASK(end_bit, start_bit));
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/* enable cache */
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syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, CACHE_ENABLE);
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}
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/**
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* @brief get aligned address and the number of cachline to be invalied
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* @param [IN] addr - start address to be invalidated
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* @param [IN] size - size in byte
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* @param [OUT] p_aligned_addr - pointer to the cacheline aligned address variable
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* @return number of cacheline to be invalidated
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*
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* * addr
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* |--------size-------------|
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* |-----|-----|-----|-----|-----|
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* \ \
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* head tail
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*
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* example 1:
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* addr = 0x100 (cacheline aligned), size = 64
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* then head = 0x100, number of cache line to be invalidated = 64 / 32 = 2
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* which means range [0x100, 0x140) will be invalidated
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*
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* example 2:
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* addr = 0x104 (cacheline unaligned), size = 64
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* then head = 0x100, number of cache line to be invalidated = 1 + 64 / 32 = 3
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* which means range [0x100, 0x160) will be invalidated
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*/
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static uint32_t get_n_cacheline(uint32_t addr, uint32_t size, uint32_t *p_head)
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{
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uint32_t n = 0;
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uint32_t tail;
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/* head */
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*p_head = CACHE_ALIGNED_ADDR(addr);
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/* roundup the tail address */
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tail = addr + size + (CACHE_LINE_SIZE - 1);
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tail = CACHE_ALIGNED_ADDR(tail);
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n = (tail - *p_head) >> CACHE_LINE_SIZE_LOG2;
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return n;
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}
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void cache_data_enable(void)
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{
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aspeed_cache_init();
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}
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void cache_data_disable(void)
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{
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const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
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syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, 0);
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}
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void cache_instr_enable(void)
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{
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aspeed_cache_init();
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}
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void cache_instr_disable(void)
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{
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const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
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syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, 0);
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}
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int cache_data_invd_all(void)
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{
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const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
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uint32_t ctrl;
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unsigned int key = 0;
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syscon_read_reg(dev, CACHE_FUNC_CTRL_REG, &ctrl);
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/* enter critical section */
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if (!k_is_in_isr()) {
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key = irq_lock();
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}
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ctrl &= ~DCACHE_CLEAN;
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syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl);
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barrier_dsync_fence_full();
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ctrl |= DCACHE_CLEAN;
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syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl);
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barrier_dsync_fence_full();
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/* exit critical section */
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if (!k_is_in_isr()) {
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irq_unlock(key);
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}
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return 0;
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}
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int cache_data_invd_range(void *addr, size_t size)
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{
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uint32_t aligned_addr, i, n;
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const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
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unsigned int key = 0;
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if (((uint32_t)addr < CACHED_SRAM_ADDR) ||
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((uint32_t)addr > CACHED_SRAM_END)) {
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return 0;
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}
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/* enter critical section */
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if (!k_is_in_isr()) {
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key = irq_lock();
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}
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n = get_n_cacheline((uint32_t)addr, size, &aligned_addr);
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for (i = 0; i < n; i++) {
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syscon_write_reg(dev, CACHE_INVALID_REG, 0);
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syscon_write_reg(dev, CACHE_INVALID_REG, DCACHE_INVALID(aligned_addr));
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aligned_addr += CACHE_LINE_SIZE;
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}
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barrier_dsync_fence_full();
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/* exit critical section */
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if (!k_is_in_isr()) {
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irq_unlock(key);
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}
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return 0;
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}
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int cache_instr_invd_all(void)
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{
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const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
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uint32_t ctrl;
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unsigned int key = 0;
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syscon_read_reg(dev, CACHE_FUNC_CTRL_REG, &ctrl);
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/* enter critical section */
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if (!k_is_in_isr()) {
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key = irq_lock();
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}
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ctrl &= ~ICACHE_CLEAN;
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syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl);
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barrier_isync_fence_full();
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ctrl |= ICACHE_CLEAN;
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syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl);
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barrier_isync_fence_full();
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/* exit critical section */
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if (!k_is_in_isr()) {
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irq_unlock(key);
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}
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return 0;
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}
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int cache_instr_invd_range(void *addr, size_t size)
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{
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uint32_t aligned_addr, i, n;
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const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
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unsigned int key = 0;
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if (((uint32_t)addr < CACHED_SRAM_ADDR) ||
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((uint32_t)addr > CACHED_SRAM_END)) {
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return 0;
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}
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n = get_n_cacheline((uint32_t)addr, size, &aligned_addr);
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/* enter critical section */
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if (!k_is_in_isr()) {
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key = irq_lock();
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}
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for (i = 0; i < n; i++) {
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syscon_write_reg(dev, CACHE_INVALID_REG, 0);
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syscon_write_reg(dev, CACHE_INVALID_REG, ICACHE_INVALID(aligned_addr));
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aligned_addr += CACHE_LINE_SIZE;
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}
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barrier_dsync_fence_full();
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/* exit critical section */
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if (!k_is_in_isr()) {
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irq_unlock(key);
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}
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return 0;
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}
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int cache_data_flush_all(void)
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{
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return -ENOTSUP;
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}
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int cache_data_flush_and_invd_all(void)
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{
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return -ENOTSUP;
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}
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int cache_data_flush_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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int cache_data_flush_and_invd_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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int cache_instr_flush_all(void)
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{
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return -ENOTSUP;
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}
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int cache_instr_flush_and_invd_all(void)
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{
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return -ENOTSUP;
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}
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int cache_instr_flush_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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int cache_instr_flush_and_invd_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
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size_t cache_data_line_size_get(void)
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{
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const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
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uint32_t ctrl;
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syscon_read_reg(dev, CACHE_FUNC_CTRL_REG, &ctrl);
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return (ctrl & CACHE_ENABLE) ? CACHE_LINE_SIZE : 0;
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}
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#endif /* CONFIG_DCACHE_LINE_SIZE_DETECT */
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#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
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size_t cache_instr_line_size_get(void)
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{
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const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
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uint32_t ctrl;
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syscon_read_reg(dev, CACHE_FUNC_CTRL_REG, &ctrl);
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return (ctrl & CACHE_ENABLE) ? CACHE_LINE_SIZE : 0;
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}
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#endif /* CONFIG_ICACHE_LINE_SIZE_DETECT */
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