51 lines
1.3 KiB
C
51 lines
1.3 KiB
C
/*
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* Copyright (c) 2022 IoT.bzh
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_RENESAS_RENESAS_CPG_MSSR_H_
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#define ZEPHYR_DRIVERS_RENESAS_RENESAS_CPG_MSSR_H_
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#ifdef CONFIG_SOC_SERIES_RCAR_GEN3
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/* Software Reset Clearing Register offsets */
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#define SRSTCLR(i) (0x940 + (i) * 4)
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/* CPG write protect offset */
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#define CPGWPR 0x900
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/* Realtime Module Stop Control Register offsets */
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static const uint16_t mstpcr[] = {
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0x110, 0x114, 0x118, 0x11c,
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0x120, 0x124, 0x128, 0x12c,
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0x980, 0x984, 0x988, 0x98c,
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};
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/* Software Reset Register offsets */
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static const uint16_t srcr[] = {
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0x0A0, 0x0A8, 0x0B0, 0x0B8,
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0x0BC, 0x0C4, 0x1C8, 0x1CC,
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0x920, 0x924, 0x928, 0x92C,
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};
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/* CAN-FD Clock Frequency Control Register */
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#define CANFDCKCR 0x244
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/* Clock stop bit */
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#define CANFDCKCR_CKSTP BIT(8)
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/* CANFD Clock */
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#define CANFDCKCR_PARENT_CLK_RATE 800000000
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#define CANFDCKCR_DIVIDER_MASK 0x1FF
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/* SCIF clock */
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#define S3D4_CLK_RATE 66600000
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#endif /* CONFIG_SOC_SERIES_RCAR_GEN3 */
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void rcar_cpg_write(uint32_t base_address, uint32_t reg, uint32_t val);
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int rcar_cpg_mstp_clock_endisable(uint32_t base_address, uint32_t bit,
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uint32_t reg, bool enable);
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#endif /* ZEPHYR_DRIVERS_RENESAS_RENESAS_CPG_MSSR_H_ */
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