84 lines
2.8 KiB
Plaintext
84 lines
2.8 KiB
Plaintext
# STM32L4, STM32L5, STM32WB and STM32WL PLL configuration options
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# Copyright (c) 2019 Linaro
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
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config CLOCK_STM32_PLL_M_DIVISOR
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int "PLL divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 1
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range 1 8 if SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
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range 1 16 if SOC_SERIES_STM32L5X
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help
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PLL divisor,
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L4: allowed values: 1-8. PLL VCO input ranges from 4 to 16MHz
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L5: allowed values: 1-16. PLL VCO input ranges from 4 to 16MHz
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WB: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz
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WL: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz
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config CLOCK_STM32_PLL_N_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 20
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range 8 86 if SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X
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range 6 127 if SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
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help
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PLL multiplier,
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L4: allowed values: 8-86. PLL VCO output ranges from 64 to 334MHz
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L5: allowed values: 8-86. PLL VCO output ranges from 64 to 334MHz
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WB: allowed values: 6-127. PLL VCO output ranges from 96 to 334MHz
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WL: allowed values: 6-127. PLL VCO output ranges from 96 to 334MHz
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config CLOCK_STM32_PLL_P_DIVISOR
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int "PLL P Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 7
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range 0 17 if SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X
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range 0 32 if SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
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help
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PLL P Output divisor
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L4: allowed values: 0, 7, 17. PLLP do not exceed 80MHz
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L5: allowed values: 0, 7, 17. PLLP do not exceed 80MHz
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WB: allowed values: 0, 2-32. PLLP do not exceed 64MHz
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WL: allowed values: 0, 2-32. PLLP do not exceed 48MHz
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config CLOCK_STM32_PLL_Q_DIVISOR
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int "PLL Q Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 0 8
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help
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PLL Q Output divisor
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L4: allowed values: 0, 2, 4, 6, 8. PLLQ do not exceed 80MHz
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L5: allowed values: 0, 2, 4, 6, 8. PLLQ do not exceed 80MHz
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WB: allowed values: 0, 2-8. PLLQ do not exceed 64MHz
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WL: allowed values: 0, 2-8. PLLQ do not exceed 48MHz
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config CLOCK_STM32_PLL_R_DIVISOR
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int "PLL R Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 4
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range 0 8
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help
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PLL R Output divisor
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L4: allowed values: 0, 2, 4, 6, 8. PLLR do not exceed 80MHz
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L5: allowed values: 0, 2, 4, 6, 8. PLLR do not exceed 110MHz
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WB: allowed values: 0, 2-8. PLLR do not exceed 64MHz
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WL: allowed values: 0, 2-8. PLLR do not exceed 48MHz
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config CLOCK_STM32_LSE
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bool "Low-speed external clock"
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help
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Enable the low-speed external (LSE) clock supplied with a 32.768 kHz
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crystal resonator oscillator.
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config CLOCK_STM32_MSI_PLL_MODE
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bool "MSI PLL MODE"
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depends on CLOCK_STM32_LSE
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help
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Enable hardware auto-calibration with LSE.
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endif # SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
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