212 lines
5.5 KiB
C
212 lines
5.5 KiB
C
/*
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Board configuration macros for Quark SE Sensor Subsystem
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*
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* This header file is used to specify and describe board-level
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* aspects for the Quark SE Sensor Subsystem.
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*/
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#ifndef _BOARD__H_
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#define _BOARD__H_
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#include <misc/util.h>
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/* default system clock */
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#define SYSCLK_DEFAULT_IOSC_HZ MHZ(32)
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/* address bases */
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#define SCSS_REGISTER_BASE 0xB0800000 /*Sensor Subsystem Base*/
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#define PERIPH_ADDR_BASE_ADC 0x80015000 /* ADC */
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#define PERIPH_ADDR_BASE_CREG_MST0 0x80018000 /* CREG Master 0 */
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#define PERIPH_ADDR_BASE_CREG_SLV0 0x80018080 /* CREG Slave 0 */
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#define PERIPH_ADDR_BASE_CREG_SLV1 0x80018180 /* CREG Slave 1 */
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#define PERIPH_ADDR_BASE_GPIO0 0x80017800 /* GPIO 0 */
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#define PERIPH_ADDR_BASE_GPIO1 0x80017900 /* GPIO 1 */
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#define PERIPH_ADDR_BASE_SPI_MST0 0x80010000 /* SPI Master 0 */
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#define PERIPH_ADDR_BASE_SPI_MST1 0x80010100 /* SPI Master 1 */
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/* IRQs */
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/* The CPU-visible IRQ numbers change between the ARC and IA cores,
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* and QMSI itself has no easy way to pick the correct one, though it
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* does have the necessary information to do it ourselves (in the meantime).
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* This macro will be used by the shim drivers to get the IRQ number to
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* use, and it should always be called using the QM_IRQ_*_INT macro
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* provided by QMSI.
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*/
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#define IRQ_GET_NUMBER(_irq) _irq##_VECTOR
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#define IRQ_TIMER0 16
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#define IRQ_TIMER1 17
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#define IRQ_I2C0_RX_AVAIL 18
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#define IRQ_I2C0_TX_REQ 19
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#define IRQ_I2C0_STOP_DET 20
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#define IRQ_I2C0_ERR 21
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#define IRQ_I2C1_RX_AVAIL 22
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#define IRQ_I2C1_TX_REQ 23
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#define IRQ_I2C1_STOP_DET 24
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#define IRQ_I2C1_ERR 25
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#define IRQ_ADC_ERR 18
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#define IRQ_ADC_IRQ 19
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#define IRQ_GPIO0_INTR 20
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#define IRQ_GPIO1_INTR 21
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#define IRQ_I2C_MST0_INTR 36
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#define IRQ_I2C_MST1_INTR 37
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#define IRQ_SPI_MST0_INTR 38
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#define IRQ_SPI_MST1_INTR 39
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#define IRQ_SPI_SLV_INTR 40
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#define IRQ_UART0_INTR 41
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#define IRQ_UART1_INTR 42
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#define IRQ_I2S_INTR 43
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#define IRQ_GPIO_INTR 44
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#define IRQ_PWM_TIMER_INTR 45
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#define IRQ_USB_INTR 46
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#define IRQ_RTC_INTR 47
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#define IRQ_WDOG_INTR 48
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#define IRQ_DMA_CHAN0 49
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#define IRQ_DMA_CHAN1 50
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#define IRQ_DMA_CHAN2 51
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#define IRQ_DMA_CHAN3 52
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#define IRQ_DMA_CHAN4 53
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#define IRQ_DMA_CHAN5 54
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#define IRQ_DMA_CHAN6 55
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#define IRQ_DMA_CHAN7 56
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#define IRQ_MAILBOXES_INTR 57
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#define IRQ_COMPARATORS_INTR 58
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#define IRQ_SYS_PMU_INTR 59
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#define IRQ_DMA_CHANS_ERR 60
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#define IRQ_INT_SRAM_CTLR 61
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#define IRQ_INT_FLASH0_CTLR 62
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#define IRQ_INT_FLASH1_CTLR 63
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#define IRQ_ALWAYS_ON_TMR 64
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#define IRQ_ADC_PWR 65
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#define IRQ_ADC_CALIB 66
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#define IRQ_ALWAYS_ON_GPIO 67
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#ifndef _ASMLANGUAGE
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#include <misc/util.h>
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#include <random/rand32.h>
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#include <quark_se/shared_mem.h>
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#define INT_ENABLE_ARC ~(0x00000001 << 8)
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#define INT_ENABLE_ARC_BIT_POS (8)
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/*
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* I2C
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*/
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#define I2C_SS_0_ERR_VECTOR 22
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#define I2C_SS_0_ERR_MASK 0x410
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#define I2C_SS_0_RX_VECTOR 23
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#define I2C_SS_0_RX_MASK 0x414
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#define I2C_SS_0_TX_VECTOR 24
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#define I2C_SS_0_TX_MASK 0x418
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#define I2C_SS_0_STOP_VECTOR 25
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#define I2C_SS_0_STOP_MASK 0x41C
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#define I2C_SS_1_ERR_VECTOR 26
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#define I2C_SS_1_ERR_MASK 0x420
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#define I2C_SS_1_RX_VECTOR 27
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#define I2C_SS_1_RX_MASK 0x424
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#define I2C_SS_1_TX_VECTOR 28
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#define I2C_SS_1_TX_MASK 0x428
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#define I2C_SS_1_STOP_VECTOR 29
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#define I2C_SS_1_STOP_MASK 0x42C
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#define DT_I2C_0_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH)
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#define DT_I2C_1_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH)
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/*
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* GPIO
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*/
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#define GPIO_DW_IO_ACCESS
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#define DT_GPIO_DW_0_BASE_ADDR 0x80017800
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#define DT_GPIO_DW_0_IRQ 20
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#define DT_GPIO_DW_0_BITS 8
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#define GPIO_DW_PORT_0_INT_MASK (SCSS_REGISTER_BASE + 0x408)
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#define DT_GPIO_DW_1_BASE_ADDR 0x80017900
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#define DT_GPIO_DW_1_IRQ 21
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#define DT_GPIO_DW_1_BITS 8
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#define GPIO_DW_PORT_1_INT_MASK (SCSS_REGISTER_BASE + 0x40C)
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#if defined(CONFIG_IOAPIC)
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#define DT_GPIO_DW_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
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#define GPIO_DW_1_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
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#else
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#define DT_GPIO_DW_0_IRQ_FLAGS 0
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#define GPIO_DW_1_IRQ_FLAGS 0
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#endif
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#define DT_GPIO_QMSI_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
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#define DT_GPIO_QMSI_1_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
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/*
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* UART
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*/
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#define DT_UART_QMSI_0_IRQ_FLAGS 0
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#define DT_UART_QMSI_1_IRQ_FLAGS 0
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/*
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* SPI
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*/
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#ifdef CONFIG_SPI_DW
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#define SPI_DW_PORT_0_ERROR_INT_MASK (SCSS_REGISTER_BASE + 0x430)
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#define SPI_DW_PORT_0_RX_INT_MASK (SCSS_REGISTER_BASE + 0x434)
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#define SPI_DW_PORT_0_TX_INT_MASK (SCSS_REGISTER_BASE + 0x438)
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#define SPI_DW_PORT_1_ERROR_INT_MASK (SCSS_REGISTER_BASE + 0x43C)
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#define SPI_DW_PORT_1_RX_INT_MASK (SCSS_REGISTER_BASE + 0x440)
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#define SPI_DW_PORT_1_TX_INT_MASK (SCSS_REGISTER_BASE + 0x444)
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#define DT_SPI_DW_IRQ_FLAGS 0
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#define SPI_DW_PORT_2_REGS 0xB0001000
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#define SPI_DW_PORT_2_IRQ IRQ_SPI_MST0_INTR
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#define SPI_DW_PORT_2_INT_MASK (SCSS_REGISTER_BASE + 0x454)
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#define SPI_DW_PORT_3_REGS 0xB0001400
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#define SPI_DW_PORT_3_IRQ IRQ_SPI_MST1_INTR
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#define SPI_DW_PORT_3_INT_MASK (SCSS_REGISTER_BASE + 0x458)
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#endif /* CONFIG_SPI_DW */
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/* Clock */
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#define CLOCK_PERIPHERAL_BASE_ADDR (SCSS_REGISTER_BASE + 0x18)
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#define CLOCK_EXTERNAL_BASE_ADDR (SCSS_REGISTER_BASE + 0x24)
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#define CLOCK_SENSOR_BASE_ADDR (SCSS_REGISTER_BASE + 0x28)
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#define CLOCK_SYSTEM_CLOCK_CONTROL (SCSS_REGISTER_BASE + \
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SCSS_CCU_SYS_CLK_CTL)
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/*
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* RTC
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*/
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#define DT_RTC_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
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static inline void quark_se_ss_ready(void)
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{
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shared_data->flags |= ARC_READY;
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}
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#endif /* !_ASMLANGUAGE */
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#endif /* _BOARD__H_ */
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