e6ebe3a8b4
The Cortex-M3/4 kernel was reserving priorities 0 and 1 for itself, but was not registering any exception on priority 0. Only reserve priority 0 and use it for SVC and fault exceptions instead of priority 1. Change-Id: Iff2405e27fd4bed4e49ab90ec2ae984f2c0a83a6 Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com> |
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arc | ||
arm | ||
nios2 | ||
x86 | ||
cpu.h |