zephyr/arch/riscv/core
Gerard Marull-Paretas a5ded8aa9f arch: riscv: smp: define MSIP_BASE
Instead of relying on definitions included indirectly.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-19 15:13:53 +00:00
..
offsets arch: riscv: offsets: fix header race condition 2024-01-19 15:13:53 +00:00
CMakeLists.txt riscv: integrate the new FPU context switching support 2023-01-24 15:26:18 +01:00
asm_macros.inc riscv: abstract RV32E register access 2022-06-23 13:12:05 -04:00
coredump.c riscv: Introduce support for RV32E 2022-06-08 18:50:22 +09:00
cpu_idle.c arch: riscv: idle: trace idle and call wfi 2024-01-12 09:58:31 +01:00
fatal.c arch: riscv: use CONFIG_RISCV_MCAUSE_EXCEPTION_MASK 2024-01-15 09:58:03 +01:00
fpu.S riscv: smarter FPU context switching support 2023-01-24 15:26:18 +01:00
fpu.c arch: smp: make flush_fpu_ipi a common, optional interfaces 2024-01-09 10:00:17 +01:00
irq_manage.c riscv: irq: Set prio for dynamic and direct irqs on clic 2024-01-18 10:53:27 +01:00
irq_offload.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
isr.S riscv: irq: Correct interrupt handling in clic non-vectored mode 2024-01-18 10:53:27 +01:00
pmp.S include: types: remove ulong_t 2022-09-06 18:16:33 +02:00
pmp.c riscv: pmp: Fix assertion for PMP misaligned start address and size 2023-10-25 10:05:24 +02:00
prep_c.c arch: riscv: define local soc_interrupt_init prototypes 2024-01-15 09:58:03 +01:00
reboot.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
reset.S arch: introduce arch_secondary_cpu_init 2024-01-09 10:00:17 +01:00
semihost.c arch: riscv: Align semihost_exec function at 16-byte boundary 2022-08-08 10:52:34 +02:00
smp.c arch: riscv: smp: define MSIP_BASE 2024-01-19 15:13:53 +00:00
switch.S riscv: integrate the new FPU context switching support 2023-01-24 15:26:18 +01:00
thread.c Revert "arch: riscv: Enable builds without the multithreading" 2023-05-26 09:04:30 -04:00
tls.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
userspace.S asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
vector_table.ld arch: riscv: core: Place vectors section through zephyr_linker_sources() 2022-09-08 10:39:31 +02:00