215 lines
6.9 KiB
C
215 lines
6.9 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2017 ARM Limited
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* Copyright (c) 2018-2019 Linaro Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* This header is originally based on mbedOS header
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* targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.h,
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* but was considerably refactored since then.
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*/
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/* This file is the re-implementation of mps2_ethernet_api and Selftest's
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* ETH_MPS2.
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* MPS2 Selftest:https://silver.arm.com/browse/VEI10 ->
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* \ISCM-1-0\AN491\software\Selftest\v2m_mps2\
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*/
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#ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_SMSC911X_PRIV_H_
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#define ZEPHYR_DRIVERS_ETHERNET_ETH_SMSC911X_PRIV_H_
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#ifndef __I
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#define __I
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#endif
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#ifndef __O
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#define __O
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#endif
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#ifndef __IO
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#define __IO
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#endif
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#define uint32_t uint32_t
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#define uint16_t uint16_t
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#define uint8_t uint8_t
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#define GET_BITFIELD(val, lsb, msb) \
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(((val) >> (lsb)) & ((1 << ((msb) - (lsb) + 1)) - 1))
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#define BFIELD(val, name) GET_BITFIELD(val, name ## _Lsb, name ## _Msb)
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#define SMSC9220_BFIELD(reg, bfield) BFIELD(SMSC9220->reg, reg ## _ ## bfield)
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/******************************************************************************/
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/* SMSC9220 Register Definitions */
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/******************************************************************************/
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typedef struct {
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/* Receive FIFO Ports (offset 0x0) */
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__I uint32_t RX_DATA_PORT;
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uint32_t RESERVED1[0x7];
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/* Transmit FIFO Ports (offset 0x20) */
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__O uint32_t TX_DATA_PORT;
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uint32_t RESERVED2[0x7];
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/* Receive FIFO status port (offset 0x40) */
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__I uint32_t RX_STAT_PORT;
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/* Receive FIFO status peek (offset 0x44) */
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__I uint32_t RX_STAT_PEEK;
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/* Transmit FIFO status port (offset 0x48) */
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__I uint32_t TX_STAT_PORT;
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/* Transmit FIFO status peek (offset 0x4C) */
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__I uint32_t TX_STAT_PEEK;
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/* Chip ID and Revision (offset 0x50) */
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__I uint32_t ID_REV;
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/* Main Interrupt Configuration (offset 0x54) */
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__IO uint32_t IRQ_CFG;
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/* Interrupt Status (offset 0x58) */
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__IO uint32_t INT_STS;
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/* Interrupt Enable Register (offset 0x5C) */
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__IO uint32_t INT_EN;
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/* Reserved for future use (offset 0x60) */
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uint32_t RESERVED3;
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/* Read-only byte order testing register 87654321h (offset 0x64) */
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__I uint32_t BYTE_TEST;
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/* FIFO Level Interrupts (offset 0x68) */
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__IO uint32_t FIFO_INT;
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/* Receive Configuration (offset 0x6C) */
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__IO uint32_t RX_CFG;
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/* Transmit Configuration (offset 0x70) */
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__IO uint32_t TX_CFG;
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/* Hardware Configuration (offset 0x74) */
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__IO uint32_t HW_CFG;
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/* RX Datapath Control (offset 0x78) */
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__IO uint32_t RX_DP_CTRL;
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/* Receive FIFO Information (offset 0x7C) */
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__I uint32_t RX_FIFO_INF;
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/* Transmit FIFO Information (offset 0x80) */
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__I uint32_t TX_FIFO_INF;
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/* Power Management Control (offset 0x84) */
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__IO uint32_t PMT_CTRL;
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/* General Purpose IO Configuration (offset 0x88) */
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__IO uint32_t GPIO_CFG;
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/* General Purpose Timer Configuration (offset 0x8C) */
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__IO uint32_t GPT_CFG;
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/* General Purpose Timer Count (offset 0x90) */
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__I uint32_t GPT_CNT;
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/* Reserved for future use (offset 0x94) */
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uint32_t RESERVED4;
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/* WORD SWAP Register (offset 0x98) */
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__IO uint32_t ENDIAN;
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/* Free Run Counter (offset 0x9C) */
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__I uint32_t FREE_RUN;
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/* RX Dropped Frames Counter (offset 0xA0) */
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__I uint32_t RX_DROP;
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/* MAC CSR Synchronizer Command (offset 0xA4) */
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__IO uint32_t MAC_CSR_CMD;
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/* MAC CSR Synchronizer Data (offset 0xA8) */
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__IO uint32_t MAC_CSR_DATA;
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/* Automatic Flow Control Configuration (offset 0xAC) */
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__IO uint32_t AFC_CFG;
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/* EEPROM Command (offset 0xB0) */
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__IO uint32_t E2P_CMD;
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/* EEPROM Data (offset 0xB4) */
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__IO uint32_t E2P_DATA;
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} SMSC9220_TypeDef;
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#define HW_CFG_SRST BIT(0)
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#define RX_STAT_PORT_PKT_LEN_Lsb 16
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#define RX_STAT_PORT_PKT_LEN_Msb 29
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#define PMT_CTRL_READY BIT(0)
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#define RX_DP_CTRL_RX_FFWD BIT(31)
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#define RX_FIFO_INF_RXSUSED_Lsb 16
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#define RX_FIFO_INF_RXSUSED_Msb 23
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#define RX_FIFO_INF_RXDUSED_Lsb 0
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#define RX_FIFO_INF_RXDUSED_Msb 15
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#define MAC_CSR_CMD_BUSY BIT(31)
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#define MAC_CSR_CMD_READ BIT(30)
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#define MAC_CSR_CMD_WRITE 0
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/* SMSC9220 MAC Registers Indices */
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#define SMSC9220_MAC_CR 0x1
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#define SMSC9220_MAC_ADDRH 0x2
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#define SMSC9220_MAC_ADDRL 0x3
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#define SMSC9220_MAC_HASHH 0x4
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#define SMSC9220_MAC_HASHL 0x5
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#define SMSC9220_MAC_MII_ACC 0x6
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#define SMSC9220_MAC_MII_DATA 0x7
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#define SMSC9220_MAC_FLOW 0x8
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#define SMSC9220_MAC_VLAN1 0x9
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#define SMSC9220_MAC_VLAN2 0xA
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#define SMSC9220_MAC_WUFF 0xB
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#define SMSC9220_MAC_WUCSR 0xC
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#define MAC_MII_ACC_MIIBZY BIT(0)
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#define MAC_MII_ACC_WRITE BIT(1)
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#define MAC_MII_ACC_READ 0
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/* SMSC9220 PHY Registers Indices */
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#define SMSC9220_PHY_BCONTROL 0
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#define SMSC9220_PHY_BSTATUS 1
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#define SMSC9220_PHY_ID1 2
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#define SMSC9220_PHY_ID2 3
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#define SMSC9220_PHY_ANEG_ADV 4
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#define SMSC9220_PHY_ANEG_LPA 5
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#define SMSC9220_PHY_ANEG_EXP 6
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#define SMSC9220_PHY_MCONTROL 17
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#define SMSC9220_PHY_MSTATUS 18
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#define SMSC9220_PHY_CSINDICATE 27
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#define SMSC9220_PHY_INTSRC 29
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#define SMSC9220_PHY_INTMASK 30
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#define SMSC9220_PHY_CS 31
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#ifndef SMSC9220_BASE
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#define SMSC9220_BASE DT_INST_REG_ADDR(0)
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#endif
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#define SMSC9220 ((volatile SMSC9220_TypeDef *)SMSC9220_BASE)
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enum smsc9220_interrupt_source {
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SMSC9220_INTERRUPT_GPIO0 = 0,
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SMSC9220_INTERRUPT_GPIO1 = 1,
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SMSC9220_INTERRUPT_GPIO2 = 2,
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SMSC9220_INTERRUPT_RXSTATUS_FIFO_LEVEL = 3,
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SMSC9220_INTERRUPT_RXSTATUS_FIFO_FULL = 4,
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/* 5 Reserved according to Datasheet */
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SMSC9220_INTERRUPT_RX_DROPPED_FRAME = 6,
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SMSC9220_INTERRUPT_TXSTATUS_FIFO_LEVEL = 7,
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SMSC9220_INTERRUPT_TXSTATUS_FIFO_FULL = 8,
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SMSC9220_INTERRUPT_TXDATA_FIFO_AVAILABLE = 9,
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SMSC9220_INTERRUPT_TXDATA_FIFO_OVERRUN = 10,
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/* 11, 12 Reserved according to Datasheet */
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SMSC9220_INTERRUPT_TRANSMIT_ERROR = 13,
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SMSC9220_INTERRUPT_RECEIVE_ERROR = 14,
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SMSC9220_INTERRUPT_RECEIVE_WATCHDOG_TIMEOUT = 15,
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SMSC9220_INTERRUPT_TXSTATUS_OVERFLOW = 16,
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SMSC9220_INTERRUPT_POWER_MANAGEMENT = 17,
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SMSC9220_INTERRUPT_PHY = 18,
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SMSC9220_INTERRUPT_GP_TIMER = 19,
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SMSC9220_INTERRUPT_RX_DMA = 20,
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SMSC9220_INTERRUPT_TX_IOC = 21,
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/* 22 Reserved according to Datasheet*/
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SMSC9220_INTERRUPT_RX_DROPPED_FRAME_HALF = 23,
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SMSC9220_INTERRUPT_RX_STOPPED = 24,
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SMSC9220_INTERRUPT_TX_STOPPED = 25,
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/* 26 - 30 Reserved according to Datasheet*/
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SMSC9220_INTERRUPT_SW = 31
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};
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#endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_SMSC911X_PRIV_H_ */
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