55 lines
1.2 KiB
Plaintext
55 lines
1.2 KiB
Plaintext
# STM32G4 PLL configuration options
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# Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_STM32G4X
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config CLOCK_STM32_PLL_M_DIVISOR
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int "PLL divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 4
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range 1 16
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help
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PLL divisor, allowed values: 1-16.
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config CLOCK_STM32_PLL_N_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 75
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range 8 127
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help
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PLL multiplier, allowed values: 8-127.
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config CLOCK_STM32_PLL_P_DIVISOR
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int "PLL P Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 7
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range 7 17
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help
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PLL P Output divisor, allowed values: 7, 17.
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config CLOCK_STM32_PLL_Q_DIVISOR
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int "PLL Q Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 2 8
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help
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PLL Q Output divisor, allowed values: 2, 4, 6, 8.
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config CLOCK_STM32_PLL_R_DIVISOR
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int "PLL R Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 2 8
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help
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PLL R Output divisor, allowed values: 2, 4, 6, 8.
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config CLOCK_STM32_LSE
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bool "Low-speed external clock"
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help
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Enable the low-speed external (LSE) clock supplied with a 32.768 kHz
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crystal resonator oscillator.
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endif # SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX
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