zephyr/soc/riscv/riscv-privilege/neorv32
Ederson de Souza d9ab35577b arch/riscv: Boot secondary CPUs for SMP support
Secondary CPUs are now initialised and made available to the system. If
the system has more CPUs than configured via CONFIG_MP_NUM_CPUS, those
are still left looping as before.

Some implementations of `soc_interrupt_init` also changed to use
`arch_irq_lock` instead of `irq_lock`.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-02-25 19:13:50 -05:00
..
CMakeLists.txt
Kconfig.defconfig.series drivers: entropy: add driver for the neorv32 trng 2021-10-26 17:53:15 -04:00
Kconfig.series
Kconfig.soc
linker.ld
reset.S
soc.c arch/riscv: Boot secondary CPUs for SMP support 2022-02-25 19:13:50 -05:00
soc.h soc: remove unnecessary inclusions of devicetree.h 2022-01-11 11:52:27 +01:00
soc_irq.S riscv: fix non-standard assembly of RISC-V 2022-02-04 11:23:39 +01:00