429 lines
11 KiB
C
429 lines
11 KiB
C
/*
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* Copyright (c) 2017-2020, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_lpc_gpio
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/** @file
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* @brief GPIO driver for LPC54XXX family
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*
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* Note:
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* - fsl_pint internally tries to manage interrupts, but this is not used (e.g.
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* s_pintCallback), Zephyr's interrupt management system is used in place.
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*/
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#include <errno.h>
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#include <device.h>
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#include <drivers/gpio.h>
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#include <soc.h>
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#include <fsl_common.h>
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#include "gpio_utils.h"
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#include <fsl_gpio.h>
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#include <fsl_pint.h>
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#include <fsl_inputmux.h>
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#include <fsl_device_registers.h>
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#define PIN_TO_INPUT_MUX_CONNECTION(port, pin) \
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((PINTSEL_PMUX_ID << PMUX_SHIFT) + (32 * port) + (pin))
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#ifndef FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS
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#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS 0
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#endif
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#ifndef FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS
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#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS 0
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#endif
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#define NO_PINT_INT \
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MAX(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS, \
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FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
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struct gpio_mcux_lpc_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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GPIO_Type *gpio_base;
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PINT_Type *pint_base;
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#ifdef IOPCTL
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IOPCTL_Type *pinmux_base;
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#else
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IOCON_Type *pinmux_base;
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#endif
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uint32_t port_no;
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clock_ip_name_t clock_ip_name;
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};
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struct gpio_mcux_lpc_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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/* pin association with PINT id */
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pint_pin_int_t pint_id[32];
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/* ISR allocated in device tree to this port */
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uint32_t isr_list[8];
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/* index to to table above */
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uint32_t isr_list_idx;
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};
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static int gpio_mcux_lpc_configure(const struct device *dev, gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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uint32_t port = config->port_no;
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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return -ENOTSUP;
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}
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#ifdef IOPCTL
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IOPCTL_Type *pinmux_base = config->pinmux_base;
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uint32_t *pinconfig = (uint32_t *)&(pinmux_base->PIO[port][pin]);
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/*
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* Enable input buffer for both input and output pins, it costs
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* nothing and allows values to be read back.
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*/
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*pinconfig |= IOPCTL_PIO_INBUF_EN;
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#endif
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if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) {
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#ifdef IOPCTL
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*pinconfig |= IOPCTL_PIO_PUPD_EN;
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if ((flags & GPIO_PULL_UP) != 0) {
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*pinconfig |= IOPCTL_PIO_PULLUP_EN;
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} else if ((flags & GPIO_PULL_DOWN) != 0) {
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*pinconfig &= ~(IOPCTL_PIO_PULLUP_EN);
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}
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#else
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IOCON_Type *pinmux_base = config->pinmux_base;
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uint32_t *pinconfig = (uint32_t *)&(pinmux_base->PIO[port][pin]);
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*pinconfig &= ~(IOCON_PIO_MODE_PULLUP|IOCON_PIO_MODE_PULLDOWN);
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if ((flags & GPIO_PULL_UP) != 0) {
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*pinconfig |= IOCON_PIO_MODE_PULLUP;
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} else if ((flags & GPIO_PULL_DOWN) != 0) {
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*pinconfig |= IOCON_PIO_MODE_PULLDOWN;
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}
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#endif
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}
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/* supports access by pin now,you can add access by port when needed */
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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gpio_base->SET[port] = BIT(pin);
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}
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if (flags & GPIO_OUTPUT_INIT_LOW) {
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gpio_base->CLR[port] = BIT(pin);
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}
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/* input-0,output-1 */
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WRITE_BIT(gpio_base->DIR[port], pin, flags & GPIO_OUTPUT);
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return 0;
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}
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static int gpio_mcux_lpc_port_get_raw(const struct device *dev,
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uint32_t *value)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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*value = gpio_base->PIN[config->port_no];
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return 0;
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}
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static int gpio_mcux_lpc_port_set_masked_raw(const struct device *dev,
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uint32_t mask,
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uint32_t value)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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uint32_t port = config->port_no;
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/* Writing 0 allows R+W, 1 disables the pin */
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gpio_base->MASK[port] = ~mask;
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gpio_base->MPIN[port] = value;
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/* Enable back the pins, user won't assume pins remain masked*/
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gpio_base->MASK[port] = 0U;
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return 0;
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}
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static int gpio_mcux_lpc_port_set_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->SET[config->port_no] = mask;
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return 0;
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}
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static int gpio_mcux_lpc_port_clear_bits_raw(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->CLR[config->port_no] = mask;
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return 0;
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}
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static int gpio_mcux_lpc_port_toggle_bits(const struct device *dev,
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uint32_t mask)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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GPIO_Type *gpio_base = config->gpio_base;
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gpio_base->NOT[config->port_no] = mask;
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return 0;
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}
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static void gpio_mcux_lpc_port_isr(const struct device *dev)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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struct gpio_mcux_lpc_data *data = dev->data;
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uint32_t enabled_int;
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uint32_t int_flags;
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uint32_t pin;
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for (pin = 0; pin < 32; pin++) {
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if (data->pint_id[pin] != NO_PINT_INT) {
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int_flags = PINT_PinInterruptGetStatus(
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config->pint_base, data->pint_id[pin]);
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enabled_int = int_flags << pin;
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PINT_PinInterruptClrStatus(config->pint_base,
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data->pint_id[pin]);
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gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
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}
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}
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}
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static uint32_t get_free_isr(struct gpio_mcux_lpc_data *data)
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{
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uint32_t i;
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uint32_t isr;
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for (i = 0; i < data->isr_list_idx; i++) {
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if (data->isr_list[i] != -1) {
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isr = data->isr_list[i];
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data->isr_list[i] = -1;
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return isr;
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}
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}
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return -EINVAL;
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}
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/* Function configures INPUTMUX device to route pin interrupts to a certain
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* PINT. PINT no. is unknown, rather it's determined from ISR no.
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*/
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static uint32_t attach_pin_to_isr(uint32_t port, uint32_t pin, uint32_t isr_no)
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{
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uint32_t pint_idx;
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/* Connect trigger sources to PINT */
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INPUTMUX_Init(INPUTMUX);
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/* Code asumes PIN_INT values are grouped [0..3] and [4..7].
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* This scenario is true in LPC54xxx/LPC55xxx.
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*/
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#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 8)
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#error having more than 8 PINT IRQs not supported in driver
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#elif (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4)
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if (isr_no < PIN_INT4_IRQn) {
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pint_idx = isr_no - PIN_INT0_IRQn;
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} else {
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pint_idx = isr_no - PIN_INT4_IRQn + 4;
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}
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#else
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pint_idx = isr_no - PIN_INT0_IRQn;
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#endif
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INPUTMUX_AttachSignal(INPUTMUX, pint_idx,
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PIN_TO_INPUT_MUX_CONNECTION(port, pin));
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/* Turnoff clock to inputmux to save power. Clock is only needed to make
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* changes. Can be turned off after.
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*/
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INPUTMUX_Deinit(INPUTMUX);
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return pint_idx;
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}
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static void gpio_mcux_lpc_port_isr(const struct device *dev);
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static int gpio_mcux_lpc_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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struct gpio_mcux_lpc_data *data = dev->data;
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pint_pin_enable_t interruptMode = kPINT_PinIntEnableNone;
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GPIO_Type *gpio_base = config->gpio_base;
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uint32_t port = config->port_no;
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uint32_t isr;
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uint32_t pint_idx;
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static bool pint_inited;
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/* Ensure pin used as interrupt is set as input*/
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if ((mode & GPIO_INT_ENABLE) &&
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((gpio_base->DIR[port] & BIT(pin)) != 0)) {
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return -ENOTSUP;
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}
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switch (mode) {
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case GPIO_INT_MODE_DISABLED:
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interruptMode = kPINT_PinIntEnableNone;
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break;
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case GPIO_INT_MODE_LEVEL:
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if (trig == GPIO_INT_TRIG_HIGH) {
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interruptMode = kPINT_PinIntEnableHighLevel;
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} else if (trig == GPIO_INT_TRIG_LOW) {
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interruptMode = kPINT_PinIntEnableLowLevel;
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} else {
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return -ENOTSUP;
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}
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break;
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case GPIO_INT_MODE_EDGE:
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if (trig == GPIO_INT_TRIG_HIGH) {
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interruptMode = kPINT_PinIntEnableRiseEdge;
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} else if (trig == GPIO_INT_TRIG_LOW) {
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interruptMode = kPINT_PinIntEnableFallEdge;
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} else {
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interruptMode = kPINT_PinIntEnableBothEdges;
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}
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break;
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default:
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return -ENOTSUP;
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}
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/* First time calling this function routes PIN->PINT->INPUTMUX->NVIC */
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if (data->pint_id[pin] == NO_PINT_INT) {
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isr = get_free_isr(data);
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if (isr == -EINVAL) {
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/* Didn't find any free interrupt in this port */
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return -EBUSY;
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}
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pint_idx = attach_pin_to_isr(port, pin, isr);
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data->pint_id[pin] = pint_idx;
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}
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if (!pint_inited) {
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PINT_Init(config->pint_base);
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pint_inited = true;
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}
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PINT_PinInterruptConfig(config->pint_base, data->pint_id[pin],
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interruptMode,
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(pint_cb_t)gpio_mcux_lpc_port_isr);
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return 0;
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}
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static int gpio_mcux_lpc_manage_cb(const struct device *port,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_mcux_lpc_data *data = port->data;
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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static int gpio_mcux_lpc_init(const struct device *dev)
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{
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const struct gpio_mcux_lpc_config *config = dev->config;
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struct gpio_mcux_lpc_data *data = dev->data;
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int i;
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GPIO_PortInit(config->gpio_base, config->port_no);
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for (i = 0; i < 32; i++) {
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data->pint_id[i] = NO_PINT_INT;
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}
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data->isr_list_idx = 0;
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return 0;
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}
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static const struct gpio_driver_api gpio_mcux_lpc_driver_api = {
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.pin_configure = gpio_mcux_lpc_configure,
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.port_get_raw = gpio_mcux_lpc_port_get_raw,
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.port_set_masked_raw = gpio_mcux_lpc_port_set_masked_raw,
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.port_set_bits_raw = gpio_mcux_lpc_port_set_bits_raw,
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.port_clear_bits_raw = gpio_mcux_lpc_port_clear_bits_raw,
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.port_toggle_bits = gpio_mcux_lpc_port_toggle_bits,
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.pin_interrupt_configure = gpio_mcux_lpc_pin_interrupt_configure,
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.manage_callback = gpio_mcux_lpc_manage_cb,
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};
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static const clock_ip_name_t gpio_clock_names[] = GPIO_CLOCKS;
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#ifdef IOPCTL
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#define PINMUX_BASE IOPCTL
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#else
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#define PINMUX_BASE IOCON
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#endif
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#define GPIO_MCUX_LPC_IRQ_CONNECT(n, m) \
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do { \
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struct gpio_mcux_lpc_data *data = dev->data; \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, m, irq), \
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DT_INST_IRQ_BY_IDX(n, m, priority), \
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gpio_mcux_lpc_port_isr, DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq)); \
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data->isr_list[data->isr_list_idx++] = DT_INST_IRQ_BY_IDX(n, m, irq); \
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} while (0)
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#define GPIO_MCUX_LPC_IRQ(n, m) \
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COND_CODE_1(DT_INST_IRQ_HAS_IDX(n, m), (GPIO_MCUX_LPC_IRQ_CONNECT(n, m)), ())
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#define GPIO_MCUX_LPC(n) \
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static int lpc_gpio_init_##n(const struct device *dev); \
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\
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static const struct gpio_mcux_lpc_config gpio_mcux_lpc_config_##n = { \
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.gpio_base = GPIO, \
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.pint_base = PINT, /* TODO: SECPINT issue #16330 */ \
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.pinmux_base = PINMUX_BASE, \
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.port_no = DT_INST_PROP(n, port), \
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.clock_ip_name = gpio_clock_names[DT_INST_PROP(n, port)], \
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}; \
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\
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static struct gpio_mcux_lpc_data gpio_mcux_lpc_data_##n; \
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\
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DEVICE_DT_INST_DEFINE(n, lpc_gpio_init_##n, NULL, \
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&gpio_mcux_lpc_data_##n, \
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&gpio_mcux_lpc_config_##n, PRE_KERNEL_1, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_mcux_lpc_driver_api); \
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\
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static int lpc_gpio_init_##n(const struct device *dev) \
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{ \
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gpio_mcux_lpc_init(dev); \
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\
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GPIO_MCUX_LPC_IRQ(n, 0); \
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GPIO_MCUX_LPC_IRQ(n, 1); \
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GPIO_MCUX_LPC_IRQ(n, 2); \
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GPIO_MCUX_LPC_IRQ(n, 3); \
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\
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return 0; \
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}
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DT_INST_FOREACH_STATUS_OKAY(GPIO_MCUX_LPC)
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