Andy Ross b76bc6c80d arch/xtensa: Fix outgoing stack flush for dummy threads ... On CPU startup, When we reach the cache flush code in arch_switch(), the outgoing thread is a dummy. The behavior of the existing code was to leave the existing value in the SR unchanged (probably NULL at startup). Then the context switch would walk from that address up to the top of the outgoing stack, flushing everything in between. That's wrong, because the outgoing stack is a real pointer (generally the interrupt stack of the current CPU), and we're flushing everything in memory underneath it. This also reverts commit 29abc8adc0 ("xtensa: fix booting secondary cores on the dummy thread"), which appears to have been an early attempt to address this issue. It worked (modulo all the extra and potentially incorrect flushing) on cavs v1.5/1.8 because of the way the entry code worked there. But on 2.5 we now hit the first context switch in a case where those extra lines are in address space already marked unwritable by the CPU, so the flush explodes. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>		2021-09-03 07:19:34 -04:00
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arc	ARC: MWDT: get rid of MWDT startup libs	2021-09-01 17:08:32 -04:00
arm	arch: arm: aarch32: Add half-precision floating-point configs	2021-08-30 18:17:47 +02:00
arm64	linker: align _image_text_start/end/size linker symbols name	2021-08-28 08:48:03 -04:00
common	arch: linker: specify intList section in the IDT_LIST region	2021-08-30 08:54:23 -04:00
nios2	…
posix	…
riscv	linker: align _image_rodata and _image_rom start/end/size linker symbols	2021-08-28 08:48:03 -04:00
sparc	SPARC: Keep interrupts disabled during kernel init	2021-07-22 10:25:53 -04:00
x86	linker: align _image_text_start/end/size linker symbols name	2021-08-28 08:48:03 -04:00
xtensa	arch/xtensa: Fix outgoing stack flush for dummy threads	2021-09-03 07:19:34 -04:00
CMakeLists.txt	…
Kconfig	kernel: demand_paging: allow reserving page frames	2021-08-26 21:16:22 -04:00