211 lines
7.1 KiB
ReStructuredText
211 lines
7.1 KiB
ReStructuredText
.. _neorv32:
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NEORV32
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#######
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Overview
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********
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The NEORV32 is an open-source RISC-V compatible processor system intended as a
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ready-to-go auxiliary processor within larger SoC designs or as a stand-alone
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customizable microcontroller.
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For more information about the NEORV32, see the following websites:
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- `The NEORV32 RISC-V Processor GitHub`_
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- `The NEORV32 RISC-V Processor Datasheet`_
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- `The NEORV32 RISC-V Processor User Guide`_
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The currently supported version is 1.8.6.
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Supported Features
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==================
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The ``neorv32`` board configuration can be used a generic definition for NEORV32
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based boards. Customisation to fit custom NEORV32 implementations can be done
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using :ref:`devicetree overlays <use-dt-overlays>`.
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Zephyr currently supports the following hardware features of the NEORV32
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Processor (SoC):
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| INTC | on-chip | interrupt controller |
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+-----------+------------+-------------------------------------+
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| MTIME | on-chip | system timer |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio, non-interrupt |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port-polling; |
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| | | serial port-interrupt |
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+-----------+------------+-------------------------------------+
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| TRNG | on-chip | entropy |
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+-----------+------------+-------------------------------------+
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The default board configuration for the NEORV32 Processor (SoC) can be found in
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the defconfig file: :file:`boards/riscv/neorv32/neorv32_defconfig`.
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System Clock
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============
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The default board configuration assumes a system clock of 100 MHz. The clock
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frequency can be overridden by changing the ``clock-frequency`` property of the
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``cpu0`` devicetree node.
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CPU
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===
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The default board configuration assumes the NEORV32 CPU implementation has the
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following RISC-V ISA extensions enabled:
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- C (Compresses Instructions)
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- M (Integer Multiplication and Division)
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- Zicsr (Control and Status Register (CSR) Instructions)
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Internal Instruction Memory
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===========================
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The default board configuration assumes the NEORV32 SoC implementation has a 64k
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byte internal instruction memory (IMEM) for code execution. The size of the
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instruction memory can be overridden by changing the ``reg`` property of the
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``imem`` devicetree node.
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Internal Data Memory
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====================
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The default board configuration assumes the NEORV32 SoC implementation has a 32k
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byte internal data memory (DMEM). The size of the data memory can be overridden
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by changing the ``reg`` property of the ``dmem`` devicetree node.
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Serial Port
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===========
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The default configuration assumes the NEORV32 SoC implements UART0 for use as
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system console.
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.. note::
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The default configuration uses a baud rate of 19200 to match that of the
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standard NEORV32 bootloader. The baudrate can be changed by modifying the
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``current-speed`` property of the ``uart0`` devicetree node.
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True Random-Number Generator
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============================
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The True Random-Number Generator (TRNG) of the NEORV32 is supported, but
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disabled by default. For NEORV32 SoC implementations supporting the TRNG,
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support can be enabled by setting the ``status`` property of the ``trng``
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devicetree node to ``okay``.
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Programming and Debugging
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*************************
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First, configure the FPGA with the NEORV32 bitstream as described in the NEORV32
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user guide.
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Next, build and flash applications as usual (see :ref:`build_an_application` and
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:ref:`application_run` for more details).
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Configuring a Console
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=====================
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Use the following settings with your serial terminal of choice (minicom, putty,
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etc.):
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- Speed: 19200
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- Data: 8 bits
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- Parity: None
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- Stop bits: 1
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Flashing via JTAG
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=================
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Here is an example for building and flashing the :ref:`hello_world` application
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for the NEORV32 via JTAG. Flashing via JTAG requires a NEORV32 SoC
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implementation with the On-Chip Debugger (OCD) and bootloader enabled.
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.. note::
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If the bootloader is not enabled, the internal instruction memory (IMEM) is
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configured as ROM which cannot be modified via JTAG.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: neorv32
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:goals: flash
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The default board configuration uses an :ref:`openocd-debug-host-tools`
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configuration similar to the example provided by the NEORV32 project. Other
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JTAGs can be used by providing further arguments when building. Here is an
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example for using the Flyswatter JTAG:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: neorv32
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:goals: flash
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:gen-args: -DBOARD_RUNNER_ARGS_openocd="--config;interface/ftdi/flyswatter.cfg;--config;neorv32.cfg;--cmd-pre-init;'adapter speed 2000'"
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After flashing, you should see message similar to the following in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build zephyr-vn.n.nn ***
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Hello World! neorv32
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Note, however, that the application was not persisted in flash memory by the
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above steps. It was merely written to internal block RAM in the FPGA. It will
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revert to the application stored in the block RAM within the FPGA bitstream
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the next time the FPGA is configured.
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The steps to persist the application within the FPGA bitstream are covered by
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the NEORV32 user guide. If the :kconfig:option:`CONFIG_BUILD_OUTPUT_BIN` is enabled and
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the NEORV32 ``image_gen`` binary is available, the build system will
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automatically generate a :file:`zephyr.vhd` file suitable for initialising the
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internal instruction memory of the NEORV32.
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In order for the build system to automatically detect the ``image_gen`` binary
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it needs to be in the :envvar:`PATH` environment variable. If not, the path
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can be passed at build time:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: neorv32
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:goals: build
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:gen-args: -DCMAKE_PROGRAM_PATH=<path/to/neorv32/sw/image_gen/>
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Uploading via UART
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==================
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If the :kconfig:option:`CONFIG_BUILD_OUTPUT_BIN` is enabled and the NEORV32
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``image_gen`` binary is available, the build system will automatically generate
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a :file:`zephyr_exe.bin` file suitable for uploading to the NEORV32 via the
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built-in bootloader as described in the NEORV32 user guide.
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Debugging via JTAG
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==================
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Here is an example for the :ref:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: neorv32
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:goals: debug
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Step through the application in your debugger, and you should see a message
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similar to the following in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build zephyr-vn.n.nn ***
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Hello World! neorv32
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.. _The NEORV32 RISC-V Processor GitHub:
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https://github.com/stnolting/neorv32
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.. _The NEORV32 RISC-V Processor Datasheet:
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https://stnolting.github.io/neorv32/
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.. _The NEORV32 RISC-V Processor User Guide:
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https://stnolting.github.io/neorv32/ug/
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