zephyr/dts/riscv/riscv32-litex-vexriscv.dtsi

/*
 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "litex,vexriscv", "litex-dev";
	model = "litex,vexriscv";


	chosen {
		zephyr,entropy = &prbs0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			clock-frequency = <100000000>;
			compatible = "spinalhdl,vexriscv", "riscv";
			device_type = "cpu";
			reg = <0>;
			riscv,isa = "rv32imac";
			status = "okay";
			timebase-frequency = <32768>;
		};
	};
	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "litex,vexriscv";
		ranges;
		intc0: interrupt-controller@bc0 {
			#interrupt-cells = <2>;
			compatible = "vexriscv,intc0";
			interrupt-controller;
			reg = <0xbc0 0x4 0xfc0 0x4>;
			reg-names = "irq_mask", "irq_pending";
			riscv,max-priority = <7>;
		};
		uart0: serial@e0001800 {
			compatible = "litex,uart0";
			interrupt-parent = <&intc0>;
			interrupts = <2 10>;
			reg = <0xe0001800 0x18>;
			reg-names = "control";
			label = "uart0";
			status = "disabled";
		};
		spi0: spi@e0002000 {
			compatible = "litex,spi";
			interrupt-parent = <&intc0>;
			interrupts = <5 0>;
			reg = <0xe0002000 0x34>;
			reg-names = "control";
			label = "spi0";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};
		timer0: timer@e0002800 {
			compatible = "litex,timer0";
			interrupt-parent = <&intc0>;
			interrupts = <1 0>;
			reg = <0xe0002800 0x40>;
			reg-names = "control";
			label = "timer0";
			status = "disabled";
		};
		eth0: ethernet@e0009800 {
			compatible = "litex,eth0";
			interrupt-parent = <&intc0>;
			interrupts = <3 0>;
			reg = <0xe0009800 0x6b 0xb0000000 0x2000>;
			local-mac-address = [10 e2 d5 00 00 02];
			reg-names = "control", "buffers";
			label = "eth0";
			status = "disabled";
		};
		dna0: dna@e0003800 {
			compatible = "litex,dna0";
			/* DNA data is 57-bits long,
			so it requires 8 bytes.
			In LiteX each 32-bit register holds
			only a single byte of meaningful data,
			hence 8 registers. */
			reg = <0xe0003800 0x20>;
			reg-names = "mem";
			label = "dna0";
			status = "disabled";
		};
		i2c0: i2c@e0005000 {
			compatible = "litex,i2c";
			reg = <0xe0005000 0x4 0xe0005004 0x4>;
			reg-names = "write", "read";
			label = "i2c0";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		gpio_out: gpio@e0005800 {
			compatible = "litex,gpio";
			reg = <0xe0005800 0x4>;
			reg-names = "control";
			ngpios = <4>;
			label = "gpio_out";
			port-is-output;
			status = "disabled";
			gpio-controller;
			#gpio-cells = <2>;
		};
		gpio_in: gpio@e0006000 {
			compatible = "litex,gpio";
			reg = <0xe0006000 0x4>;
			reg-names = "control";
			ngpios = <4>;
			label = "gpio_in";
			status = "disabled";
			gpio-controller;
			#gpio-cells = <2>;
		};
		prbs0: prbs@e0006800 {
			compatible = "litex,prbs";
			reg = <0xe0006800 0x4>;
			reg-names = "status";
			label = "prbs0";
			status = "disabled";
		};
		pwm0: pwm@e0007000 {
			compatible = "litex,pwm";
			reg = <0xe0007000 0x4 0xe0007004 0x10 0xe0007014 0x10>;
			reg-names = "enable", "width", "period";
			label = "pwm0";
			status = "disabled";
			#pwm-cells = <2>;
		};
		i2s_rx: i2s_rx@e000a800 {
			compatible = "litex,i2s";
			reg = <0xe000a800 0x20 0xb1000000 0x40000>;
			interrupt-parent = <&intc0>;
			interrupts = <6 2>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg-names = "control", "fifo";
			fifo_depth = <256>;
			label = "i2s_rx";
			status = "disabled";
		};
		i2s_tx: i2s_tx@e000b000 {
			compatible = "litex,i2s";
			reg = <0xe000b000 0x20 0xb2000000 0x40000>;
			interrupt-parent = <&intc0>;
			interrupts = <7 2>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg-names = "control", "fifo";
			fifo_depth = <256>;
			label = "i2s_tx";
			status = "disabled";
		};
		clock-outputs {
			#address-cells = <1>;
			#size-cells = <0>;
			clk0: clock-controller@0 {
				#clock-cells = <1>;
				reg = <0>;
				compatible = "litex,clkout";
				clock-output-names = "CLK_0";
				litex,clock-frequency = <100000000>;
				litex,clock-phase = <0>;
				litex,clock-duty-num = <1>;
				litex,clock-duty-den = <2>;
				litex,clock-margin = <1>;
				litex,clock-margin-exp = <2>;
				status = "disabled";
			};
			clk1: clock-controller@1 {
				#clock-cells = <1>;
				reg = <1>;
				compatible = "litex,clkout";
				clock-output-names = "CLK_1";
				litex,clock-frequency = <100000000>;
				litex,clock-phase = <0>;
				litex,clock-duty-num = <1>;
				litex,clock-duty-den = <2>;
				litex,clock-margin = <1>;
				litex,clock-margin-exp = <2>;
				status = "disabled";
			};
		};
		clock0: clock@82005000 {
			compatible = "litex,clk";
			label = "clock0";
			reg = <0x82005000 0x1
			       0x82005004 0x1
			       0x82005008 0x1
			       0x8200500c 0x1
			       0x82005010 0x1
			       0x82005014 0x1
			       0x82005018 0x2
			       0x82005020 0x2>;
			reg-names = "drp_reset",
				    "drp_locked",
				    "drp_read",
				    "drp_write",
				    "drp_drdy",
				    "drp_adr",
				    "drp_dat_w",
				    "drp_dat_r";
			#clock-cells = <1>;
			clocks = <&clk0 0>, <&clk1 1>;
			clock-output-names = "CLK_0", "CLK_1";
			litex,lock-timeout = <10>;
			litex,drdy-timeout = <10>;
			litex,sys-clock-frequency = <100000000>;
			litex,divclk-divide-min = <1>;
			litex,divclk-divide-max = <107>;
			litex,clkfbout-mult-min = <2>;
			litex,clkfbout-mult-max = <65>;
			litex,vco-freq-min = <600000000>;
			litex,vco-freq-max = <1200000000>;
			litex,clkout-divide-min = <1>;
			litex,clkout-divide-max = <126>;
			litex,vco-margin = <0>;
			status = "disabled";
		};
	};
};