96 lines
2.9 KiB
C
96 lines
2.9 KiB
C
/*
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* Copyright (c) 2021 Katsuhiro Suzuki
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/sys/util.h>
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#include "prci.h"
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BUILD_ASSERT(MHZ(1000) == DT_PROP(DT_NODELABEL(coreclk), clock_frequency),
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"Unsupported CORECLK frequency");
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BUILD_ASSERT(KHZ(125125) == DT_PROP(DT_NODELABEL(pclk), clock_frequency),
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"Unsupported PCLK frequency");
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static inline void wait_controller_cycle(void)
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{
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/* HACK to get the '1 full controller clock cycle'. */
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__asm__ volatile ("fence");
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}
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/*
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* Switch the clock source
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* - core: to 1GHz PLL (CORE_PLL) from 26MHz oscillator (HFCLK)
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* - peri: to 250MHz PLL (HFPCLKPLL) from HFCLK
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* - ddr: to 923MHz PLL (DDRPLL) from HFCLK (half of the data rate)
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* on the HiFive Unmatched board.
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*
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* Note: Valid PLL VCO range is 2400MHz to 4800MHz
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*/
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static int fu740_clock_init(void)
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{
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PRCI_REG(PRCI_COREPLLCFG) =
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PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */
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PLL_F(76) | /* VCO: 2 x (76 + 1) = 154 = 4004MHz */
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PLL_Q(2) | /* output divider: VCO / 2^2 = 1001MHz */
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PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */
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PLL_BYPASS(PLL_BYPASS_DISABLE) |
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PLL_FSE(PLL_FSE_INTERNAL);
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while ((PRCI_REG(PRCI_COREPLLCFG) & PLL_LOCK(1)) == 0)
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;
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/* Switch CORE_CLK to CORE_PLL from HFCLK */
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PRCI_REG(PRCI_COREPLLSEL) = COREPLLSEL_SEL(COREPLLSEL_COREPLL);
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PRCI_REG(PRCI_CORECLKSEL) = CLKSEL_SEL(CLKSEL_PLL);
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PRCI_REG(PRCI_HFPCLKPLLCFG) =
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PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */
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PLL_F(76) | /* VCO: 2 x (76 + 1) = 154 = 4004MHz */
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PLL_Q(4) | /* output divider: VCO / 2^4 = 250.25MHz */
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PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */
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PLL_BYPASS(PLL_BYPASS_DISABLE) |
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PLL_FSE(PLL_FSE_INTERNAL);
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while ((PRCI_REG(PRCI_HFPCLKPLLCFG) & PLL_LOCK(1)) == 0)
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;
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/* Switch PCLK to HFPCLKPLL/2 from HFCLK/2 */
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PRCI_REG(PRCI_HFPCLKPLLOUTDIV) = OUTDIV_PLLCKE(OUTDIV_PLLCKE_ENA);
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PRCI_REG(PRCI_HFPCLKPLLSEL) = CLKSEL_SEL(CLKSEL_PLL);
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PRCI_REG(PRCI_DDRPLLCFG) =
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PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */
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PLL_F(70) | /* VCO: 2 x (70 + 1) = 154 = 1872MHz */
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PLL_Q(2) | /* output divider: VCO / 2^2 = 936MHz */
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PLL_RANGE(PLL_RANGE_18MHZ) |
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PLL_BYPASS(PLL_BYPASS_DISABLE) |
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PLL_FSE(PLL_FSE_INTERNAL);
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while ((PRCI_REG(PRCI_DDRPLLCFG) & PLL_LOCK(1)) == 0)
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;
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PRCI_REG(PRCI_DDRPLLOUTDIV) |= OUTDIV_PLLCKE(OUTDIV_PLLCKE_ENA);
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PRCI_REG(PRCI_DEVICESRESETN) |= DEVICERESETN_DDRCTRL;
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wait_controller_cycle();
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/* Release DDR reset */
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PRCI_REG(PRCI_DEVICESRESETN) |= DEVICERESETN_DDRAXI |
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DEVICERESETN_DDRAHB |
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DEVICERESETN_DDRPHY;
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wait_controller_cycle();
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/*
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* These take like 16 cycles to actually propagate. We can't go sending stuff before they
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* come out of reset. So wait.
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*/
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for (int i = 0; i < 256; i++) {
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__asm__ volatile ("nop");
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}
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return 0;
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}
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SYS_INIT(fu740_clock_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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