170 lines
3.9 KiB
C
170 lines
3.9 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @brief Driver for UART port on STM32F10x family processor.
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*
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* Based on reference manual:
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* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
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* advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 27: Universal synchronous asynchronous receiver
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* transmitter (USART)
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*/
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#ifndef _STM32_UART_H_
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#define _STM32_UART_H_
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/* 27.6.1 Status register (USART_SR) */
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union __sr {
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uint32_t val;
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struct {
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uint32_t pe :1 __packed;
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uint32_t fe :1 __packed;
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uint32_t ne :1 __packed;
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uint32_t ore :1 __packed;
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uint32_t idle :1 __packed;
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uint32_t rxne :1 __packed;
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uint32_t tc :1 __packed;
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uint32_t txe :1 __packed;
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uint32_t lbd :1 __packed;
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uint32_t cts :1 __packed;
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uint32_t rsvd__10_15 : 6 __packed;
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uint32_t rsvd__16_31 : 16 __packed;
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} bit;
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};
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/* 27.6.2 Data register (USART_DR) */
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union __dr {
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uint32_t val;
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struct {
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uint32_t dr :8 __packed;
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uint32_t rsvd__9_31 :24 __packed;
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} bit;
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};
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/* 27.6.3 Baud rate register (USART_BRR) */
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union __brr {
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uint32_t val;
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struct {
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uint32_t fraction :4 __packed;
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uint32_t mantissa :12 __packed;
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uint32_t rsvd__16_31 :16 __packed;
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} bit;
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};
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/* 27.6.4 Control register 1 (USART_CR1) */
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union __cr1 {
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uint32_t val;
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struct {
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uint32_t sbk :1 __packed;
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uint32_t rwu :1 __packed;
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uint32_t re :1 __packed;
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uint32_t te :1 __packed;
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uint32_t idleie :1 __packed;
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uint32_t rxneie :1 __packed;
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uint32_t tcie :1 __packed;
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uint32_t txeie :1 __packed;
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uint32_t peie :1 __packed;
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uint32_t ps :1 __packed;
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uint32_t pce :1 __packed;
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uint32_t wake :1 __packed;
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uint32_t m :1 __packed;
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uint32_t ue :1 __packed;
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uint32_t rsvd__14_15 :2 __packed;
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uint32_t rsvd__16_31 :16 __packed;
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} bit;
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};
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/* 27.6.5 Control register 2 (USART_CR2) */
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union __cr2 {
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uint32_t val;
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struct {
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uint32_t addr :4 __packed;
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uint32_t rsvd__4 :1 __packed;
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uint32_t lbdl :1 __packed;
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uint32_t lbdie :1 __packed;
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uint32_t rsvd__7 :1 __packed;
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uint32_t lbcl :1 __packed;
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uint32_t cpha :1 __packed;
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uint32_t cpol :1 __packed;
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uint32_t clken :1 __packed;
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uint32_t stop :2 __packed;
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uint32_t linen :1 __packed;
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uint32_t rsvd__15_31 :17 __packed;
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} bit;
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};
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/* 27.6.6 Control register 3 (USART_CR3) */
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union __cr3 {
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uint32_t val;
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struct {
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uint32_t eie :1 __packed;
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uint32_t iren :1 __packed;
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uint32_t irlp :1 __packed;
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uint32_t hdsel :1 __packed;
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uint32_t nack :1 __packed;
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uint32_t scen :1 __packed;
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uint32_t dmar :1 __packed;
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uint32_t dmat :1 __packed;
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uint32_t rtse :1 __packed;
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uint32_t ctse :1 __packed;
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uint32_t ctsie :1 __packed;
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uint32_t rsvd__11_31 :21 __packed;
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} bit;
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};
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/* 27.6.7 Guard time and prescaler register (USART_GTPR) */
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union __gtpr {
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uint32_t val;
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struct {
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uint32_t psc :8 __packed;
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uint32_t gt :8 __packed;
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uint32_t rsvd__16_31 :16 __packed;
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} bit;
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};
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/* 27.6.8 USART register map */
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struct uart_stm32 {
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union __sr sr;
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union __dr dr;
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union __brr brr;
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union __cr1 cr1;
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union __cr2 cr2;
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union __cr3 cr3;
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union __gtpr gtpr;
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};
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/* device config */
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struct uart_stm32_config {
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struct uart_device_config uconf;
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/* clock subsystem driving this peripheral */
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clock_control_subsys_t clock_subsys;
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};
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/* driver data */
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struct uart_stm32_data {
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/* current baud rate */
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uint32_t baud_rate;
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/* clock device */
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struct device *clock;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_t user_cb;
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#endif
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};
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#endif /* _STM32_UART_H_ */
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