Tomasz Bursztyka 5e4e0298e9 arch/x86: Generalize cache manipulation functions ... We assume that all x86 CPUs do have clflush instructions. And the cache line size is now provided through DTS. So detecting clflush instruction as well as the cache line size is no longer required at runtime and thus removed. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>		2021-02-15 09:43:30 -05:00
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doc	boards: x86: Remove gpmrb board	2020-07-30 12:15:01 -04:00
CMakeLists.txt	x86: remove memory mapping SOC code	2020-07-17 11:38:18 +02:00
Kconfig.defconfig	arch/x86: Generalize cache manipulation functions	2021-02-15 09:43:30 -05:00
Kconfig.soc	x86: reserve the first megabyte	2021-01-23 19:47:23 -05:00
cpu.c	zephyr: replace zephyr integer types with C99 types	2020-06-08 08:23:57 -05:00
linker.ld	x86: add common memory.ld	2020-09-30 14:14:07 -07:00
soc.h	arch/x86: early_serial cleanup	2020-07-08 12:34:09 +02:00
soc_gpio.h	drivers: gpio: gpio_intel_apl: Convert to DT_INST	2020-04-20 15:23:11 -05:00