Fabio Baltieri bd5ea8d552 dts: ite: move pinctrl subdevices up a node ... Refactor the pinctrl nodes slightly so that the port devices are not child of the main pinctrl node. This is because the pinctrl node is being used as parent for pinctrl setting nodes itself, and having the port nodes as child end up creating a circular depdency with the edt child enumeration patch. Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>		2023-10-25 18:39:31 -07:00
..
andes	drivers: dma: Add Andestech atcdmac300 driver.	2023-10-20 14:51:08 +02:00
efinix	drivers: intc: plic: define all registers' offset in the driver	2023-10-04 09:06:28 -04:00
espressif/esp32c3	dts: bindings: can: deprecate the sjw and sjw-data properties	2023-09-28 16:28:56 +02:00
gigadevice	dts/riscv: add missing `riscv,isa` fields and modify existing ones	2023-09-14 14:34:34 +02:00
ite	dts: ite: move pinctrl subdevices up a node	2023-10-25 18:39:31 -07:00
lowrisc	drivers: intc: plic: define all registers' offset in the driver	2023-10-04 09:06:28 -04:00
microchip	drivers: intc: plic: define all registers' offset in the driver	2023-10-04 09:06:28 -04:00
niosv	dts: riscv: niosv: Fix status string	2023-09-19 15:23:36 +01:00
openisa	dts/riscv: add missing `riscv,isa` fields and modify existing ones	2023-09-14 14:34:34 +02:00
sifive	drivers: intc: plic: define all registers' offset in the driver	2023-10-04 09:06:28 -04:00
starfive	drivers: intc: plic: define all registers' offset in the driver	2023-10-04 09:06:28 -04:00
telink	drivers: intc: plic: define all registers' offset in the driver	2023-10-04 09:06:28 -04:00
neorv32.dtsi	dts/riscv: add missing `riscv,isa` fields and modify existing ones	2023-09-14 14:34:34 +02:00
riscv32-litex-vexriscv.dtsi	dts/riscv: add missing `riscv,isa` fields and modify existing ones	2023-09-14 14:34:34 +02:00
virt.dtsi	board: riscv: qemu: increase ndev of PLIC to 1024	2023-10-05 06:10:06 -04:00