zephyr/arch
Jean-Paul Etienne 34862656b9 riscv32: fixed context restore upon exiting ISR
By now, t0 register restored value is overwritten
by mepc and mstatus values prior to returning from ISR.

Fixed by restoring mstatus and mepc registers before
restoring the caller-saved registers.

As t0 is a temporary register within the riscv ABI,
this issue was unnoticed for most applications, except
for computation intensive apps, like crypto tests.

Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-06-30 06:31:51 -04:00
..
arc linker: move all linker headers to include/linker 2017-06-18 09:24:04 -05:00
arm tests: boot_time: cleanup boot_time test to work on ARM 2017-06-29 07:08:59 -04:00
common linker: move all linker headers to include/linker 2017-06-18 09:24:04 -05:00
nios2 linker: move all linker headers to include/linker 2017-06-18 09:24:04 -05:00
riscv32 riscv32: fixed context restore upon exiting ISR 2017-06-30 06:31:51 -04:00
x86 qemu_x86: ia32: fix ROM size with XIP enabled 2017-06-29 07:46:58 -04:00
xtensa arch: xtensa: Use CONFIG_SIMULATOR_XTENSA to set XT_{BOARD,SIMULATOR} 2017-06-21 18:09:13 -04:00
Kconfig spell: Kconfig help typos: /arch 2017-04-24 20:14:53 +00:00
Makefile gen_isr_tables: New static interrupt build mechanism 2017-02-11 01:27:58 +00:00