48 lines
1013 B
C
48 lines
1013 B
C
/*
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* Copyright (c) 2018 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32WB processor
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/logging/log.h>
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#include <stm32_ll_system.h>
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#include <cmsis_core.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(soc);
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extern void stm32_pm_init(void);
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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*/
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void soc_early_init_hook(void)
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{
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/* Enable the ART Accelerator I-cache, D-cache and prefetch */
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LL_FLASH_EnableInstCache();
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LL_FLASH_EnableDataCache();
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LL_FLASH_EnablePrefetch();
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 4 MHz from MSI */
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SystemCoreClock = 4000000;
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/* Set C2 Power Mode to shutdown */
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/* It will be updated by C2 when required */
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LL_C2_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
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#if CONFIG_PM
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stm32_pm_init();
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#endif
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}
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