97 lines
2.7 KiB
C
97 lines
2.7 KiB
C
/*
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* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
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* Copyright (c) 2019 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32G0 processor
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/linker/linker-defs.h>
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#include <string.h>
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#include <cmsis_core.h>
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#include <stm32_ll_system.h>
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#if defined(SYSCFG_CFGR1_UCPD1_STROBE) || defined(SYSCFG_CFGR1_UCPD2_STROBE)
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#include <stm32_ll_bus.h>
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#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
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/**
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* @brief Disable the internal Pull-Up in Dead Battery pins of UCPD peripherals
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*
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* The internal Pull-Up in Dead Battery pins of UCPD peripherals are disabled,
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* unless the UCPD driver and the corresponding peripheral is enabled. In that
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* case this will be taken care of by the driver.
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*/
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static void stm32g0_disable_dead_battery(void)
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{
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#if defined(SYSCFG_CFGR1_UCPD1_STROBE) || defined(SYSCFG_CFGR1_UCPD2_STROBE)
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uint32_t strobe = 0;
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#if defined(CONFIG_USBC_TCPC_STM32)
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#define DT_DRV_COMPAT st_stm32_ucpd
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#define DEV_REG_ADDR_INIT(n) addr_inst[n] = DT_INST_REG_ADDR(n);
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uint32_t addr_inst[DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT)];
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DT_INST_FOREACH_STATUS_OKAY(DEV_REG_ADDR_INIT);
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#else
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uint32_t addr_inst[0];
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#endif
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#if defined(SYSCFG_CFGR1_UCPD1_STROBE)
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strobe |= LL_SYSCFG_UCPD1_STROBE;
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#endif /* SYSCFG_CFGR1_UCPD1_STROBE */
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#if defined(SYSCFG_CFGR1_UCPD2_STROBE)
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strobe |= LL_SYSCFG_UCPD2_STROBE;
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#endif /* SYSCFG_CFGR1_UCPD2_STROBE */
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for (int n = 0; n < ARRAY_SIZE(addr_inst); n++) {
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#if defined(SYSCFG_CFGR1_UCPD1_STROBE) && defined(UCPD1_BASE)
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if (addr_inst[n] == UCPD1_BASE) {
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strobe &= ~LL_SYSCFG_UCPD1_STROBE;
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}
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#endif /* SYSCFG_CFGR1_UCPD1_STROBE && UCPD1_BASE */
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#if defined(SYSCFG_CFGR1_UCPD2_STROBE) && defined(UCPD2_BASE)
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if (addr_inst[n] == UCPD2_BASE) {
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strobe &= ~LL_SYSCFG_UCPD2_STROBE;
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}
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#endif /* SYSCFG_CFGR1_UCPD2_STROBE && UCPD2_BASE */
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}
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if (strobe != 0) {
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
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LL_SYSCFG_DisableDBATT(strobe);
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}
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#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
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}
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extern void stm32_power_init(void);
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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*/
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void soc_early_init_hook(void)
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{
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/* Enable ART Accelerator I-cache and prefetch */
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LL_FLASH_EnableInstCache();
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LL_FLASH_EnablePrefetch();
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 16 MHz from HSI */
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SystemCoreClock = 16000000;
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/* Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */
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stm32g0_disable_dead_battery();
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#if CONFIG_PM
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stm32_power_init();
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#endif
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}
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