49 lines
1.6 KiB
C
49 lines
1.6 KiB
C
/*
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* Copyright (c) 2024 Nordic Semiconductor ASA.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
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#define USBHS_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(usbhs), core)
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#define USBHS_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(usbhs), core)
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#define CAN120_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(can120), message_ram)
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#define CAN120_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), message_ram) + \
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DT_REG_SIZE_BY_NAME(DT_NODELABEL(can120), m_can)
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#define CAN121_BASE DT_REG_ADDR_BY_NAME(DT_NODELABEL(can121), message_ram)
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#define CAN121_SIZE DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), message_ram) + \
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DT_REG_SIZE_BY_NAME(DT_NODELABEL(can121), m_can)
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static struct arm_mpu_region mpu_regions[] = {
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MPU_REGION_ENTRY("FLASH_0",
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CONFIG_FLASH_BASE_ADDRESS,
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REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS,
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CONFIG_FLASH_SIZE * 1024)),
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MPU_REGION_ENTRY("SRAM_0",
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CONFIG_SRAM_BASE_ADDRESS,
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REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS,
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CONFIG_SRAM_SIZE * 1024)),
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usbhs))
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MPU_REGION_ENTRY("USBHS_CORE", USBHS_BASE,
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REGION_RAM_NOCACHE_ATTR(USBHS_BASE, USBHS_SIZE)),
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(can120))
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MPU_REGION_ENTRY("CAN120_MCAN", CAN120_BASE,
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REGION_RAM_NOCACHE_ATTR(CAN120_BASE, CAN120_SIZE)),
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(can121))
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MPU_REGION_ENTRY("CAN121_MCAN", CAN121_BASE,
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REGION_RAM_NOCACHE_ATTR(CAN121_BASE, CAN121_SIZE)),
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#endif
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};
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const struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};
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