zephyr/soc/xtensa/esp32s2
Glauber Maroto Ferreira 31e5b1b861 soc: esp32s2: fix: data cache setup
data cache mode setup and enabling should be done only when
CONFIG_ESP_SPIRAM is enabled. Otherwise, memory layout will
conflict with defaults.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-12-03 16:45:16 -06:00
..
include
CMakeLists.txt soc: esp32s2: refactor cache and bss initialization 2021-11-20 11:57:38 -05:00
Kconfig.defconfig
Kconfig.soc esp32 & esp32s2: lint: kconfig 2021-11-22 08:31:56 -05:00
linker.ld soc: esp32s2: add SPI RAM support 2021-11-20 11:57:38 -05:00
soc.c soc: esp32s2: fix: data cache setup 2021-12-03 16:45:16 -06:00
soc.h soc: esp32s2: refactor cache and bss initialization 2021-11-20 11:57:38 -05:00
soc_cache.c soc: esp32s2: refactor cache and bss initialization 2021-11-20 11:57:38 -05:00