87 lines
1.5 KiB
Plaintext
87 lines
1.5 KiB
Plaintext
/*
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* Copyright (c) 2018, Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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//#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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#define DT_APB_CLK_HZ 100000000
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "snps,arcem";
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reg = <0>;
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};
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intc: arcv2-intc {
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compatible = "snps,arcv2-intc";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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iccm0: iccm@60000000 {
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compatible = "arc,iccm";
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reg = <0x60000000 0x20000>;
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};
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dccm0: dccm@80000000 {
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compatible = "arc,dccm";
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reg = <0x80000000 0x20000>;
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};
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/* this is (Psuedo SRAM), so treat it like mmio-sram */
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sram0: memory@10000000 {
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compatible = "mmio-sram";
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reg = <0x10000000 0x1000000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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uart0: uart@f0004000 {
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compatible = "ns16550";
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clock-frequency = <DT_APB_CLK_HZ>;
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reg = <0xf0004000 0x1000>;
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label = "UART_0";
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interrupt-parent = <&intc>;
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};
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gpio0: gpio@f0002000 {
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compatible = "snps,designware-gpio";
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reg = <0xf0002000 0xc>;
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ngpios = <4>;
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label = "GPIO_0";
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interrupt-parent = <&intc>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@f000200c {
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compatible = "snps,designware-gpio";
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reg = <0xf000200c 0xc>;
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ngpios = <8>;
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label = "GPIO_1";
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interrupt-parent = <&intc>;
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interrupts = <0 1>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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