60 lines
1.7 KiB
Plaintext
60 lines
1.7 KiB
Plaintext
# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "ITE IT8XXX2 system implementation"
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depends on SOC_SERIES_RISCV32_IT8XXX2
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config SOC_IT8XXX2
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bool "ITE IT8XXX2 system implementation"
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select RISCV
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select ATOMIC_OPERATIONS_BUILTIN
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_C
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endchoice
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if SOC_IT8XXX2
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config SOC_IT8XXX2_PLL_FLASH_48M
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bool "Flash frequency is 48MHz"
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default y
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help
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Change frequency of PLL, CPU, and flash to 48MHz during initialization.
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Set n to use the default settings.
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(PLL and CPU run at 48MHz, flash frequency is 16MHz)
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config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
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bool "The pins of GPIO group K and L aren't bonding with pad"
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default y
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help
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On IT81202 (128-pins package), the pins of GPIO group K and L aren't
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bonding with pad. So we configure these pins as internal pull-down
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at default to prevent leakage current due to floating.
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config SOC_IT8XXX2_GPIO_H7_DEFAULT_OUTPUT_LOW
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bool "The GPIOH7 isn't bonding with pad and is left floating internally"
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default y
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help
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On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left
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floating internally. We need to enable internal pull-down for the pin
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to prevent leakage current, but IT81202/IT81302 doesn't have the
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capability to pull it down. We can only set it as output low,
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so we enable output low for it at initialization to prevent leakage.
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choice
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prompt "Clock source for PLL reference clock"
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config SOC_IT8XXX2_INT_32K
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bool "Use the +/-2.3% internal clock generator"
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config SOC_IT8XXX2_EXT_32K
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bool "Use external 32.768 kHz clock source"
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endchoice
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endif # SOC_IT8XXX2
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