Carlo Caione 10061efdc4 riscv: Rework and cleanup Kconfig ... This patch is doing several things: - Core ISA and extension Kconfig symbols have now a formalized name (CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*) - a new Kconfig.isa file was introduced with the full set of extensions currently supported by the v2.2 spec - a new Kconfig.core file was introduced to host all the RISCV cores (currently only E31) - ISA and extensions settings are moved to SoC configuration files Signed-off-by: Carlo Caione <ccaione@baylibre.com>		2022-06-05 14:28:42 +02:00
..
arc	doc: toolchains: Add Zephyr SDK documentation	2022-06-01 15:26:48 +02:00
arm	soc: pm: Microchip MEC172x SoC based power management	2022-06-05 14:28:25 +02:00
arm64	…
common	boards: xtensa: Activate the intel_adsp west runner	2022-06-05 14:13:57 +02:00
mips	…
nios2	…
posix	include: add more missing zephyr/ prefixes	2022-05-27 15:20:27 -07:00
riscv	riscv: Rework and cleanup Kconfig	2022-06-05 14:28:42 +02:00
shields	include: add more missing zephyr/ prefixes	2022-05-27 15:20:27 -07:00
sparc	…
x86	…
xtensa	soc: cavs: add a README to document the usage	2022-06-05 14:13:57 +02:00
CMakeLists.txt	…
Kconfig	…
deprecated.cmake	…
index.rst	…