108 lines
2.4 KiB
ArmAsm
108 lines
2.4 KiB
ArmAsm
/*
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* Copyright (c) 2022 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/arch/cpu.h>
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#include "asm_macros.inc"
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#define CSR_PMPCFG_BASE 0x3a0
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#define CSR_PMPADDR_BASE 0x3b0
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/*
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* Prototype:
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*
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* void z_riscv_write_pmp_entries(unsigned int start, // a0
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* unsigned int end, // a1
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* bool clear_trailing_entries, // a2
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* ulong_t *pmp_addr, // a3
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* ulong_t *pmp_cfg) // a4
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*
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* Called from pmp.c to write a range of PMP entries.
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*
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* PMP registers are accessed with the csr instruction which only takes an
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* immediate value as the actual register. In order to avoid traversing
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* the whole register list, we use the start index to jump directly to the
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* location corresponding to the start of the wanted range. For this to work
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* we disallow compressed instructions so the update block sizes are easily
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* known (luckily they're all power-of-2's simplifying the code further).
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*
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* start < end && end <= CONFIG_PMP_SLOTS must be true.
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*/
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GTEXT(z_riscv_write_pmp_entries)
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SECTION_FUNC(TEXT, z_riscv_write_pmp_entries)
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la t0, pmpaddr_store
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slli t1, a0, 4 /* 16-byte instruction blocks */
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add t0, t0, t1
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jr t0
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pmpaddr_store:
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.option push
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.option norvc
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.set _index, 0
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.rept CONFIG_PMP_SLOTS
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lr t0, (RV_REGSIZE * _index)(a3)
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li t1, _index + 1
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csrw (CSR_PMPADDR_BASE + _index), t0
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beq t1, a1, pmpaddr_done
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.set _index, _index + 1
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.endr
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.option pop
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pmpaddr_done:
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/*
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* Move to the pmpcfg space:
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* a0 = a0 / RV_REGSIZE
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* a1 = (a1 + RV_REGSIZE - 1) / RV_REGSIZE
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*/
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la t0, pmpcfg_store
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srli a0, a0, RV_REGSHIFT
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slli t1, a0, 4 /* 16-byte instruction blocks */
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add t0, t0, t1
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addi a1, a1, RV_REGSIZE - 1
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srli a1, a1, RV_REGSHIFT
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jr t0
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pmpcfg_store:
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.option push
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.option norvc
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.set _index, 0
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.rept (CONFIG_PMP_SLOTS / RV_REGSIZE)
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lr t0, (RV_REGSIZE * _index)(a4)
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addi a0, a0, 1
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csrw (CSR_PMPCFG_BASE + RV_REGSIZE/4 * _index), t0
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beq a0, a1, pmpcfg_done
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.set _index, _index + 1
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.endr
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.option pop
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pmpcfg_done:
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beqz a2, done
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la t0, pmpcfg_zerotail
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slli a0, a0, 2 /* 4-byte instruction blocks */
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add t0, t0, a0
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jr t0
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pmpcfg_zerotail:
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.option push
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.option norvc
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.set _index, 0
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.rept (CONFIG_PMP_SLOTS / RV_REGSIZE)
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csrw (CSR_PMPCFG_BASE + RV_REGSIZE/4 * _index), zero
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.set _index, _index + 1
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.endr
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.option pop
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done: ret
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