395 lines
9.9 KiB
Plaintext
395 lines
9.9 KiB
Plaintext
# ARC options
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# Copyright (c) 2014, 2019 Wind River Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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menu "ARC Options"
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depends on ARC
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config ARCH
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default "arc"
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config CPU_ARCEM
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bool
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select ATOMIC_OPERATIONS_C
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help
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This option signifies the use of an ARC EM CPU
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config CPU_ARCHS
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bool
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select ATOMIC_OPERATIONS_BUILTIN
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help
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This option signifies the use of an ARC HS CPU
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choice
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prompt "ARC Instruction Set"
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default ISA_ARCV2
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config ISA_ARCV2
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bool "ARC ISA v2"
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select ARCH_HAS_STACK_PROTECTION if ARC_HAS_STACK_CHECKING || (ARC_MPU && ARC_MPU_VER !=2)
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select ARCH_HAS_USERSPACE if ARC_MPU
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select USE_SWITCH
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select USE_SWITCH_SUPPORTED
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help
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v2 ISA for the ARC-HS & ARC-EM cores
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config ISA_ARCV3
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bool "ARC ISA v3"
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select USE_SWITCH
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select USE_SWITCH_SUPPORTED
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endchoice
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if ISA_ARCV2
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config CPU_EM4
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bool
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select CPU_ARCEM
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help
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If y, the SoC uses an ARC EM4 CPU
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config CPU_EM4_DMIPS
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bool
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select CPU_ARCEM
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help
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If y, the SoC uses an ARC EM4 DMIPS CPU
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config CPU_EM4_FPUS
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bool
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select CPU_ARCEM
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help
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If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision
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floating-point extension
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config CPU_EM4_FPUDA
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bool
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select CPU_ARCEM
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help
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If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision
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floating-point and double assist instructions
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config CPU_EM6
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bool
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select CPU_ARCEM
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help
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If y, the SoC uses an ARC EM6 CPU
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config CPU_HS3X
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bool
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select CPU_ARCHS
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help
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If y, the SoC uses an ARC HS3x or HS4x CPU
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endif #ISA_ARCV2
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if ISA_ARCV3
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config CPU_HS5X
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bool
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select CPU_ARCHS
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help
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If y, the SoC uses an ARC HS6x CPU
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config CPU_HS6X
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bool
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select CPU_ARCHS
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select 64BIT
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help
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If y, the SoC uses an ARC HS6x CPU
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endif #ISA_ARCV3
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config FP_FPU_DA
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bool
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menu "ARC CPU Options"
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config ARC_HAS_ZOL
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bool
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depends on ISA_ARCV2
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default y
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help
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ARCv2 CPUs have ZOL hardware loop mechanism which the ARCv3 ISA drops.
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Architecturally ZOL provides
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- LPcc instruction
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- LP_COUNT core reg
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- LP_START, LP_END aux regs
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Disabling this option removes usage of ZOL regs from code
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config NUM_IRQ_PRIO_LEVELS
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int "Number of supported interrupt priority levels"
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range 1 16
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help
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Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1.
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The minimum value is 1.
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The BSP must provide a valid default for proper operation.
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config NUM_IRQS
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int "Upper limit of interrupt numbers/IDs used"
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range 17 256
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help
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Interrupts available will be 0 to NUM_IRQS-1.
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The minimum value is 17 as the first 16 entries in the vector
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table are for CPU exceptions.
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The BSP must provide a valid default. This drives the size of the
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vector table.
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config RGF_NUM_BANKS
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int "Number of General Purpose Register Banks"
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depends on ARC_FIRQ
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depends on NUM_IRQ_PRIO_LEVELS > 1
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range 1 2
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default 2
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help
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The ARC CPU can be configured to have more than one register
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bank. If fast interrupts are supported (FIRQ), the 2nd
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register bank, in the set, will be used by FIRQ interrupts.
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If fast interrupts are supported but there is only 1
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register bank, the fast interrupt handler must save
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and restore general purpose registers.
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NOTE: it's required to have more than one interrupt priority level
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to use second register bank - otherwise all interrupts will use
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same register bank. Such configuration isn't supported in software
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and it is not beneficial from the performance point of view.
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config ARC_FIRQ
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bool "FIRQ enable"
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depends on ISA_ARCV2
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depends on NUM_IRQ_PRIO_LEVELS > 1
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default y
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help
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Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts
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with highest priority, status32 and pc will be saved in aux regs,
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other regs will be saved according to the number of register bank;
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If FIRQ is disabled, the handle of interrupts with highest priority
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will be same with other interrupts.
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NOTE: we don't allow the configuration with FIRQ enabled and only one
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interrupt priority level (so all interrupts are FIRQ). Such
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configuration isn't supported in software and it is not beneficial
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from the performance point of view.
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config ARC_FIRQ_STACK
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bool "Separate firq stack"
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depends on ARC_FIRQ && RGF_NUM_BANKS > 1
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help
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Use separate stack for FIRQ handing. When the fast irq is also a direct
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irq, this will get the minimal interrupt latency.
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config ARC_FIRQ_STACK_SIZE
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int "FIRQ stack size"
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depends on ARC_FIRQ_STACK
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default 1024
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help
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The size of firq stack.
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config ARC_HAS_STACK_CHECKING
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bool "ARC has STACK_CHECKING"
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depends on ISA_ARCV2
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default y
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help
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ARC is configured with STACK_CHECKING which is a mechanism for
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checking stack accesses and raising an exception when a stack
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overflow or underflow is detected.
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config ARC_CONNECT
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bool "ARC has ARC connect"
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select SCHED_IPI_SUPPORTED
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help
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ARC is configured with ARC CONNECT which is a hardware for connecting
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multi cores.
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config ARC_STACK_CHECKING
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bool
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select NO_UNUSED_STACK_INSPECTION
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help
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Use ARC STACK_CHECKING to do stack protection
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config ARC_STACK_PROTECTION
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bool
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default y if HW_STACK_PROTECTION
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select ARC_STACK_CHECKING if ARC_HAS_STACK_CHECKING
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select MPU_STACK_GUARD if (!ARC_STACK_CHECKING && ARC_MPU && ARC_MPU_VER !=2)
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select THREAD_STACK_INFO
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help
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This option enables either:
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- The ARC stack checking, or
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- the MPU-based stack guard
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to cause a system fatal error
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if the bounds of the current process stack are overflowed.
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The two stack guard options are mutually exclusive. The
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selection of the ARC stack checking is
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prioritized over the MPU-based stack guard.
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config ARC_USE_UNALIGNED_MEM_ACCESS
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bool "Unaligned access in HW"
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default y if CPU_ARCHS
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depends on (CPU_ARCEM && !ARC_HAS_SECURE) || CPU_ARCHS
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help
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ARC EM cores w/o secure shield 2+2 mode support might be configured
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to support unaligned memory access which is then disabled by default.
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Enable unaligned access in hardware and make software to use it.
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config FAULT_DUMP
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int "Fault dump level"
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default 2
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range 0 2
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help
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Different levels for display information when a fault occurs.
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2: The default. Display specific and verbose information. Consumes
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the most memory (long strings).
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1: Display general and short information. Consumes less memory
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(short strings).
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0: Off.
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config GEN_ISR_TABLES
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default y
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config GEN_IRQ_START_VECTOR
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default 16
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config HARVARD
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bool "Harvard Architecture"
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help
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The ARC CPU can be configured to have two busses;
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one for instruction fetching and another that serves as a data bus.
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config CODE_DENSITY
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bool "Code Density Option"
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help
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Enable code density option to get better code density
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config ARC_HAS_ACCL_REGS
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bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
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default y if CPU_HS3X
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help
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Depending on the configuration, CPU can contain accumulator reg-pair
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(also referred to as r58:r59). These can also be used by gcc as GPR so
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kernel needs to save/restore per process
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config ARC_HAS_SECURE
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bool "ARC has SecureShield"
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depends on ISA_ARCV2
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select CPU_HAS_TEE
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select ARCH_HAS_TRUSTED_EXECUTION
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help
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This option is enabled when ARC core supports secure mode
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config SJLI_TABLE_SIZE
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int "SJLI table size"
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depends on ARC_SECURE_FIRMWARE
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default 8
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help
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The size of sjli (Secure Jump and Link Indexed) table. The
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code in normal mode call secure services in secure mode through
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sjli instruction.
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config ARC_SECURE_FIRMWARE
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bool "Generate Secure Firmware"
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depends on ARC_HAS_SECURE
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default y if TRUSTED_EXECUTION_SECURE
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help
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This option indicates that we are building a Zephyr image that
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is intended to execute in secure mode. The option is only
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applicable to ARC processors that implement the SecureShield.
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This option enables Zephyr to include code that executes in
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secure mode, as well as to exclude code that is designed to
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execute only in normal mode.
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Code executing in secure mode has access to both the secure
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and normal resources of the ARC processors.
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config ARC_NORMAL_FIRMWARE
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bool "Generate Normal Firmware"
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depends on !ARC_SECURE_FIRMWARE
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depends on ARC_HAS_SECURE
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default y if TRUSTED_EXECUTION_NONSECURE
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help
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This option indicates that we are building a Zephyr image that
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is intended to execute in normal mode. Execution of this
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image is triggered by secure firmware that executes in secure
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mode. The option is only applicable to ARC processors that
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implement the SecureShield.
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This option enables Zephyr to include code that executes in
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normal mode only, as well as to exclude code that is
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designed to execute only in secure mode.
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Code executing in normal mode has no access to secure
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resources of the ARC processors, and, therefore, it shall avoid
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accessing them.
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menu "ARC MPU Options"
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depends on CPU_HAS_MPU
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config ARC_MPU_ENABLE
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bool "Memory Protection Unit (MPU)"
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select ARC_MPU
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help
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Enable MPU
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source "arch/arc/core/mpu/Kconfig"
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endmenu
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config DCACHE_LINE_SIZE
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default 32
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config ARC_EXCEPTION_STACK_SIZE
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int "ARC exception handling stack size"
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default 768 if !64BIT
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default 2048 if 64BIT
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help
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Size in bytes of exception handling stack which is at the top of
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interrupt stack to get smaller memory footprint because exception
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is not frequent. To reduce the impact on interrupt handling,
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especially nested interrupt, it cannot be too large.
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endmenu
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config ARC_EXCEPTION_DEBUG
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bool "Unhandled exception debugging information"
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default n
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depends on PRINTK || LOG
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help
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Print human-readable information about exception vectors, cause codes,
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and parameters, at a cost of code/data size for the human-readable
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strings.
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endmenu
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config MAIN_STACK_SIZE
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default 4096 if 64BIT
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config ISR_STACK_SIZE
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default 4096 if 64BIT
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config SYSTEM_WORKQUEUE_STACK_SIZE
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default 4096 if 64BIT
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config IDLE_STACK_SIZE
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default 1024 if 64BIT
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config IPM_CONSOLE_STACK_SIZE
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default 2048 if 64BIT
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config TEST_EXTRA_STACK_SIZE
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default 2048 if 64BIT
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config CMSIS_THREAD_MAX_STACK_SIZE
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default 2048 if 64BIT
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config CMSIS_V2_THREAD_MAX_STACK_SIZE
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default 2048 if 64BIT
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config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE
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default 2048 if 64BIT
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