294 lines
9.0 KiB
C
294 lines
9.0 KiB
C
/*
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* Copyright (c) 2022 Vestas Wind Systems A/S
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* Copyright (c) 2022 Blue Clover
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/can.h>
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#include <zephyr/drivers/can/can_mcan.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <stm32_ll_rcc.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include <zephyr/sys/util.h>
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LOG_MODULE_REGISTER(can_stm32h7, CONFIG_CAN_LOG_LEVEL);
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#define DT_DRV_COMPAT st_stm32h7_fdcan
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/* This symbol takes the value 1 if one of the device instances */
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/* is configured in dts with a domain clock */
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#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
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#define STM32H7_FDCAN_DOMAIN_CLOCK_SUPPORT 1
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#else
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#define STM32H7_FDCAN_DOMAIN_CLOCK_SUPPORT 0
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#endif
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#define VOS0_MAX_FREQ MHZ(125)
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struct can_stm32h7_config {
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mm_reg_t base;
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mem_addr_t mrba;
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mem_addr_t mram;
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void (*config_irq)(void);
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const struct pinctrl_dev_config *pcfg;
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size_t pclk_len;
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const struct stm32_pclken *pclken;
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uint8_t clock_divider;
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};
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static int can_stm32h7_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
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return can_mcan_sys_read_reg(stm32h7_cfg->base, reg, val);
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}
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static int can_stm32h7_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
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return can_mcan_sys_write_reg(stm32h7_cfg->base, reg, val);
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}
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static int can_stm32h7_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
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return can_mcan_sys_read_mram(stm32h7_cfg->mram, offset, dst, len);
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}
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static int can_stm32h7_write_mram(const struct device *dev, uint16_t offset, const void *src,
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size_t len)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
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return can_mcan_sys_write_mram(stm32h7_cfg->mram, offset, src, len);
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}
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static int can_stm32h7_clear_mram(const struct device *dev, uint16_t offset, size_t len)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
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return can_mcan_sys_clear_mram(stm32h7_cfg->mram, offset, len);
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}
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static int can_stm32h7_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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const uint32_t rate_tmp = LL_RCC_GetFDCANClockFreq(LL_RCC_FDCAN_CLKSOURCE);
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uint32_t cdiv;
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ARG_UNUSED(dev);
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if (rate_tmp == LL_RCC_PERIPH_FREQUENCY_NO) {
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LOG_ERR("Can't read core clock");
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return -EIO;
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}
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cdiv = FIELD_GET(FDCANCCU_CCFG_CDIV, FDCAN_CCU->CCFG);
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if (cdiv == 0U) {
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*rate = rate_tmp;
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} else {
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*rate = rate_tmp / (cdiv << 1U);
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}
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return 0;
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}
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static int can_stm32h7_clock_enable(const struct device *dev)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
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const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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uint32_t fdcan_clock = 0xffffffff;
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int ret;
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if (!device_is_ready(clk)) {
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LOG_ERR("clock control device not ready");
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return -ENODEV;
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}
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if (IS_ENABLED(STM32H7_FDCAN_DOMAIN_CLOCK_SUPPORT) && (stm32h7_cfg->pclk_len > 1)) {
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ret = clock_control_configure(clk,
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(clock_control_subsys_t)&stm32h7_cfg->pclken[1],
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NULL);
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if (ret < 0) {
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LOG_ERR("Could not select can_stm32fd domain clock");
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return ret;
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}
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/* Check if clock has correct range according to chosen regulator voltage
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* scaling (Table 62 of RM0399 Rev 4).
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* There is no need to test HSE case, since it's value is in range of
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* 4 to 50 MHz (please refer to CubeMX clock control).
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*/
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ret = clock_control_get_rate(clk,
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(clock_control_subsys_t)&stm32h7_cfg->pclken[1], &fdcan_clock);
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if (ret != 0) {
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LOG_ERR("failure getting clock rate");
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return ret;
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}
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if (fdcan_clock > VOS0_MAX_FREQ) {
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LOG_ERR("FDCAN Clock source %d exceeds max allowed %d",
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fdcan_clock, VOS0_MAX_FREQ);
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return -ENODEV;
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}
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}
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ret = clock_control_on(clk, (clock_control_subsys_t)&stm32h7_cfg->pclken[0]);
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if (ret != 0) {
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LOG_ERR("failure enabling clock");
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return ret;
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}
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if (stm32h7_cfg->clock_divider != 0U) {
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can_mcan_enable_configuration_change(dev);
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FDCAN_CCU->CCFG = FDCANCCU_CCFG_BCC |
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FIELD_PREP(FDCANCCU_CCFG_CDIV, stm32h7_cfg->clock_divider >> 1U);
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}
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return 0;
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}
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static int can_stm32h7_init(const struct device *dev)
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{
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const struct can_mcan_config *mcan_cfg = dev->config;
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const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
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int ret;
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/* Configure dt provided device signals when available */
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ret = pinctrl_apply_state(stm32h7_cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret != 0) {
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LOG_ERR("CAN pinctrl setup failed (%d)", ret);
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return ret;
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}
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ret = can_stm32h7_clock_enable(dev);
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if (ret != 0) {
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return ret;
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}
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ret = can_mcan_configure_mram(dev, stm32h7_cfg->mrba, stm32h7_cfg->mram);
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if (ret != 0) {
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return ret;
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}
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ret = can_mcan_init(dev);
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if (ret != 0) {
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return ret;
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}
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stm32h7_cfg->config_irq();
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return 0;
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}
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static const struct can_driver_api can_stm32h7_driver_api = {
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.get_capabilities = can_mcan_get_capabilities,
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.start = can_mcan_start,
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.stop = can_mcan_stop,
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.set_mode = can_mcan_set_mode,
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.set_timing = can_mcan_set_timing,
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.send = can_mcan_send,
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.add_rx_filter = can_mcan_add_rx_filter,
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.remove_rx_filter = can_mcan_remove_rx_filter,
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.get_state = can_mcan_get_state,
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#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
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.recover = can_mcan_recover,
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#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE*/
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.get_core_clock = can_stm32h7_get_core_clock,
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.get_max_filters = can_mcan_get_max_filters,
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.set_state_change_callback = can_mcan_set_state_change_callback,
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/* Timing limits are per the STM32H7 Reference Manual (RM0433 Rev 7),
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* section 56.5.7, FDCAN nominal bit timing and prescaler register
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* (FDCAN_NBTP).
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*
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* Beware that the reference manual contains a bug regarding the minimum
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* values for nominal phase segments. Valid register values are 1 and up.
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*/
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.timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
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.timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
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#ifdef CONFIG_CAN_FD_MODE
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.set_timing_data = can_mcan_set_timing_data,
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/* Data timing limits are per the STM32H7 Reference Manual
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* (RM0433 Rev 7), section 56.5.3, FDCAN data bit timing and prescaler
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* register (FDCAN_DBTP).
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*/
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.timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
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.timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
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#endif
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};
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static const struct can_mcan_ops can_stm32h7_ops = {
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.read_reg = can_stm32h7_read_reg,
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.write_reg = can_stm32h7_write_reg,
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.read_mram = can_stm32h7_read_mram,
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.write_mram = can_stm32h7_write_mram,
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.clear_mram = can_stm32h7_clear_mram,
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};
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#define CAN_STM32H7_MCAN_INIT(n) \
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CAN_MCAN_DT_INST_BUILD_ASSERT_MRAM_CFG(n); \
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BUILD_ASSERT(CAN_MCAN_DT_INST_MRAM_ELEMENTS_SIZE(n) <= \
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CAN_MCAN_DT_INST_MRAM_SIZE(n), \
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"Insufficient Message RAM size to hold elements"); \
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\
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static void stm32h7_mcan_irq_config_##n(void); \
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\
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PINCTRL_DT_INST_DEFINE(n); \
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CAN_MCAN_DT_INST_CALLBACKS_DEFINE(n, can_stm32h7_cbs_##n); \
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\
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static const struct stm32_pclken can_stm32h7_pclken_##n[] = \
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STM32_DT_INST_CLOCKS(n); \
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\
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static const struct can_stm32h7_config can_stm32h7_cfg_##n = { \
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.base = CAN_MCAN_DT_INST_MCAN_ADDR(n), \
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.mrba = CAN_MCAN_DT_INST_MRBA(n), \
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.mram = CAN_MCAN_DT_INST_MRAM_ADDR(n), \
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.config_irq = stm32h7_mcan_irq_config_##n, \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.pclken = can_stm32h7_pclken_##n, \
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.pclk_len = DT_INST_NUM_CLOCKS(n), \
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.clock_divider = DT_INST_PROP_OR(n, clk_divider, 0) \
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}; \
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\
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static const struct can_mcan_config can_mcan_cfg_##n = \
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CAN_MCAN_DT_CONFIG_INST_GET(n, &can_stm32h7_cfg_##n, \
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&can_stm32h7_ops, \
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&can_stm32h7_cbs_##n); \
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\
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static struct can_mcan_data can_mcan_data_##n = \
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CAN_MCAN_DATA_INITIALIZER(NULL); \
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\
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CAN_DEVICE_DT_INST_DEFINE(n, can_stm32h7_init, NULL, \
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&can_mcan_data_##n, \
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&can_mcan_cfg_##n, \
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POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
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&can_stm32h7_driver_api); \
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\
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static void stm32h7_mcan_irq_config_##n(void) \
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{ \
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LOG_DBG("Enable CAN inst" #n " IRQ"); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, int0, irq), \
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DT_INST_IRQ_BY_NAME(n, int0, priority), \
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can_mcan_line_0_isr, DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(n, int0, irq)); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, int1, irq), \
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DT_INST_IRQ_BY_NAME(n, int1, priority), \
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can_mcan_line_1_isr, DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(n, int1, irq)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(CAN_STM32H7_MCAN_INIT)
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