116 lines
2.5 KiB
Plaintext
116 lines
2.5 KiB
Plaintext
# Copyright 2019,2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_LPC55XXX
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select HAS_MCUX
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select HAS_MCUX_FLEXCOMM
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select HAS_MCUX_SYSCON
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select HAS_MCUX_WWDT
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_DWT
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select PLATFORM_SPECIFIC_INIT
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config SOC_LPC55S06
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE
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select HAS_MCUX_RNG
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config SOC_LPC55S16
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE
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select HAS_MCUX_MCAN
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select HAS_MCUX_RNG
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config SOC_LPC55S28
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select HAS_MCUX_IAP
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select HAS_MCUX_LPADC
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select HAS_MCUX_LPC_DMA
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select HAS_MCUX_RNG
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config SOC_LPC55S36
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select HAS_MCUX_MCAN
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select HAS_MCUX_PWM
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config SOC_LPC55S69
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select CPU_CORTEX_M33
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config SOC_LPC55S69_CPU0
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select HAS_MCUX_IAP
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select HAS_MCUX_LPADC
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select HAS_MCUX_LPC_DMA
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select HAS_MCUX_USB_LPCIP3511
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select HAS_MCUX_CTIMER
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select HAS_MCUX_SCTIMER
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select HAS_MCUX_RNG
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select HAS_PM
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if SOC_SERIES_LPC55XXX
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config INIT_PLL0
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bool "Initialize PLL0"
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config INIT_PLL1
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bool "Initialize PLL1"
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default "y"
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depends on !(SOC_LPC55S06 || FLASH || BUILD_WITH_TFM)
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help
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In the LPC55XXX Family, this is currently being used to set the
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core clock value at it's highest frequency which clocks at 150MHz.
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Note that flash programming operations are limited to 100MHz, and
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this PLL should not be used as the core clock in those cases.
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config SECOND_CORE_MCUX
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bool "LPC55xxx's second core"
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config SECOND_CORE_BOOT_ADDRESS_MCUX
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depends on SECOND_CORE_MCUX
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hex "Address the second core will boot at"
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))
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help
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This is the address the second core will boot from.
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config LPC55XXX_SRAM_CLOCKS
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bool "CLock LPC SRAM banks"
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config LPC55XXX_USB_RAM
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bool
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if SOC_LPC55S69
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config SOC_FLASH_MCUX
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bool
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endif # SOC_LPC55S69
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config MCUX_CORE_SUFFIX
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default "_cm33_core0" if SOC_LPC55S69_CPU0
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default "_cm33_core1" if SOC_LPC55S69_CPU1
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endif # SOC_SERIES_LPC55XXX
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