142 lines
3.5 KiB
C
142 lines
3.5 KiB
C
/*
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright (c) 2018 Prevas A/S
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* Copyright (c) 2019 Thomas Burdick <thomas.burdick@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for fsl_frdm_k22f platform
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*
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* This module provides routines to initialize and support board-level
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* hardware for the fsl_frdm_k22f platform.
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/drivers/uart.h>
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#include <fsl_common.h>
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#include <fsl_clock.h>
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#include <zephyr/arch/cpu.h>
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#include <cmsis_core.h>
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#define TIMESRC_OSCERCLK (2)
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#define CLOCK_NODEID(clk) \
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DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
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#define CLOCK_DIVIDER(clk) \
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DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
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static const osc_config_t oscConfig = {
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.freq = CONFIG_OSC_XTAL0_FREQ,
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.capLoad = 0,
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#if defined(CONFIG_OSC_EXTERNAL)
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.workMode = kOSC_ModeExt,
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#elif defined(CONFIG_OSC_LOW_POWER)
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.workMode = kOSC_ModeOscLowPower,
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#elif defined(CONFIG_OSC_HIGH_GAIN)
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.workMode = kOSC_ModeOscHighGain,
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#else
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#error "An oscillator mode must be defined"
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#endif
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.oscerConfig = {
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.enableMode = 0U, /* Disable external reference clock */
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#if FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER
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.erclkDiv = 0U,
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#endif
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},
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};
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static const mcg_pll_config_t pll0Config = {
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.enableMode = 0U,
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.prdiv = CONFIG_MCG_PRDIV0,
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.vdiv = CONFIG_MCG_VDIV0,
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};
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static const sim_clock_config_t simConfig = {
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.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
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.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
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SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
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SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
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SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
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};
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/**
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*
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* @brief Initialize the system clock
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*
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* This routine will configure the multipurpose clock generator (MCG) to
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* set up the system clock.
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* The MCG has nine possible modes, including Stop mode. This routine assumes
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* that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
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* It transitions through the FLL Bypassed External (FBE) and
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* PLL Bypassed External (PBE) modes to get to the desired
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* PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
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* clock.
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*
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*/
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static ALWAYS_INLINE void clock_init(void)
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{
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CLOCK_SetSimSafeDivs();
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CLOCK_InitOsc0(&oscConfig);
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CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
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CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
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CONFIG_MCG_FCRDIV);
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/* Configure FLL external reference divider (FRDIV). */
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CLOCK_SetFllExtRefDiv(0);
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CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
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CLOCK_SetSimConfig(&simConfig);
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#if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS
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CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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#endif
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}
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/**
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*
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* @brief Perform basic hardware initialization
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*
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* Initialize the interrupt controller device drivers.
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* Also initialize the timer device driver, if required.
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*
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* @return 0
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*/
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static int fsl_frdm_k22f_init(void)
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{
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/* release I/O power hold to allow normal run state */
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PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
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/* Initialize PLL/system clock to 120 MHz */
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clock_init();
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return 0;
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}
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#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
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void z_arm_platform_init(void)
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{
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SystemInit();
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}
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#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
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SYS_INIT(fsl_frdm_k22f_init, PRE_KERNEL_1, 0);
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